Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ Creator & Designer Forum Discussions

Anonymous
Not applicable

Hello everyone,

I am trying to build a custom component using verilog on psoc creator 3.3 but after finishing my code writing and during building I am getting errors. Is there any difference in terms of syntax in psoc creator's verilog and general verilog?

I have attached my project along with pdf which I am using as a reference guide. 

http://www.cypress.com/file/42156/download

0 Likes
1 Solution
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Initialization of outputs not possible, must be done with hardware signals.

   

 

   

Bob

View solution in original post

0 Likes
4 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Initialization of outputs not possible, must be done with hardware signals.

   

 

   

Bob

0 Likes
Anonymous
Not applicable

Thanks for your help.
What about internal reg cnt? I also cant initialize it. 😞
So, the only solution is to add a reset button to initialize all the outputs and internal regs and to do so i have to bring MCU in loop as well to generate reset pulse after some delay?

   


 

0 Likes
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Isn't that your reset condition?
always @(posedge clk or negedge rst) begin
if(rst==0)begin
cnt<=0;
p1<=0;
p2<=1;
s1<=0;
s2<=1;
end

   

 

   

Bob

Anonymous
Not applicable

Yeah, it is but still i have to generate negedge from MCU after some delay to reset my component at start. Before I was thinking of making my component without reset button and initialize everything at the start while declaring them as regs. But later I came to know that it isnt possible in PSoC's verilog and you confirmed it as well while debugging my code.   

0 Likes