I am trying to build a custom component using verilog on psoc creator 3.3 but after finishing my code writing and during building I am getting errors. Is there any difference in terms of syntax in psoc creator's verilog and general verilog?
I have attached my project along with pdf which I am using as a reference guide.
Solved! Go to Solution.
Thanks for your help.
What about internal reg cnt? I also cant initialize it. 😞
So, the only solution is to add a reset button to initialize all the outputs and internal regs and to do so i have to bring MCU in loop as well to generate reset pulse after some delay?
Isn't that your reset condition?
always @(posedge clk or negedge rst) begin
Yeah, it is but still i have to generate negedge from MCU after some delay to reset my component at start. Before I was thinking of making my component without reset button and initialize everything at the start while declaring them as regs. But later I came to know that it isnt possible in PSoC's verilog and you confirmed it as well while debugging my code.