Mar 13, 2013
09:27 AM
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Mar 13, 2013
09:27 AM
The counter component does not have the ability to unselect the presence of an Enable. It is always
shown. If enable is tied logically high, always enabled, does clock spec meet 49.2 Mhz for Vdd >= 4.75 V ?
Datasheet a little confusing on this.
Regards, dana.
4 Replies
Mar 13, 2013
09:28 AM
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Mar 13, 2013
09:28 AM
29466I is the part of interest.
Regards, Dana.
Mar 13, 2013
02:41 PM
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Mar 13, 2013
02:41 PM
The answer is if enable tied high, higher frequency at 5V applies.
Main datasheet, should be reflected in it, conditions that is.
Regards, Dana.
Anonymous
Not applicable
Mar 14, 2013
07:50 PM
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Mar 14, 2013
07:50 PM
Hi Dana-san, Where did the AC specs came from? According to counter data sheet v2.5, Maximum input frequency is 48MHz at VDD=5.0, regardless using of Enable-signal. When I using the counter, It's work well upto 50MHz actually. Happy 29466!
Mar 15, 2013
06:04 AM
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Mar 15, 2013
06:04 AM
29466I datasheet in Designer Device Documents. AC specs.
Regards, Dana.