Hi there,
I'm trying to make a custom component written in Verilog which uses a Control Register and Status Register for interacting with C firmware. However, the API for both the status and control registers aren't generated, but I've noticed this is not an issue when using the UDB Editor instead? I've included an example project which showcases the issue with the Control Register, the same happens when a Status Register is instantiated in the component's verilog (the status register API shown below is from the TopDesign schematic, not the custom component).
As shown below, the component contains a control register but the associated API is not generated.
I'm using PSoC Creator 4.4 and the target device is a PSoC 3.
Also, not quite related, but for the status and control registers there seems to be no include guard for either registers so they get defined multiple times if there are multiple components using them (or in the TopDesign)? I've gotten around this by removing the includes in my verilog when necessary. Is there an existing macro defined somewhere to ifndef the includes with in my own verilog files?
Thanks in advance!
Hi @MK22
I guess the observation made by you is valid. This is because when you are using a UDB Editor to add a control or status register it uses the Status and Control register component by Cypress.
If you drag and drop a control register component on your top design and build the project then you would notice that the same set of .c and .h files are generated. The UDB Editor guide also mentions the same.
However, in your project in the Verilog file for the custom component, you have created I observed that you have included only the .v file for the control register library. So the .c and .h files would not be generated.
Kindly let me know in case of any clarifications or if my understanding of the issue is not correct.
Best Regards
Ekta
