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smirnsky
Level 1
Level 1
5 sign-ins First reply posted First question asked

my team and I have try to build bootloader and application code with cy8c6136fdi-f42.

I modified dfu_cm4_app0.ld, dfu_cm4_app1.ld file to divide 512kb memory area into bootloader and application code.

and modified  makefile referring  document like link LINKER_SCRIPT or POSTBUILD and etc...

document : [ ../mtb_shared/dfu/releasev4.20.0/docs/dfu_sdk_api_reference_manual/html/index.html ]

however, both app0 and app1 can be built, but when I try to upload the code to mcu using miniprog, it gets an error.

====================================================================================

[MODUS LOG]

Started by GNU MCU Eclipse
Open On-Chip Debugger 0.11.0+dev-4.3.0.1746 (2021-09-16-07:59)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
adapter speed: 2000 kHz
adapter srst delay: 25
adapter srst pulse_width: 25
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
cortex_m reset_config sysresetreq
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : Using CMSIS-DAPv2 interface with VID:PID=0x04b4:0xf151, serial=201714D101310400
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: JTAG supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.30.1155
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 2.830 V
Info : kitprog3: acquiring the device (mode: reset)...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x6ba02477
Info : psoc6.cpu.cm4: hardware has 6 breakpoints, 4 watchpoints
***************************************
** Silicon: 0xE235, Family: 0x100, Rev.: 0x23 (B2)
** Detected Device: CY8C6136FDI-F42
** Detected Main Flash size, kb: 512
** Flash Boot version: 1.20.1.42
** Chip Protection: NORMAL
***************************************
Info : starting gdb server for psoc6.cpu.cm4 on 3333
Info : Listening on port 3333 for gdb connections
Info : SWD DPIDR 0x6ba02477
psoc6.cpu.cm4 halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x00000f00 msp: 0x08047800
Started by GNU MCU Eclipse
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
Warn : Prefer GDB command "target extended-remote :3333" instead of "target remote :3333"
semihosting is enabled
Warn : No RTOS could be auto-detected!
Warn : No RTOS could be auto-detected!
Info : All data matches, Flash programming skipped
Info : SWD DPIDR 0x6ba02477
Info : Halt timed out, wake up GDB.
Error: timed out while waiting for target halted
Info : Halt timed out, wake up GDB.
Error: timed out while waiting for target halted

====================================================================================

What is the cause?

thank you !

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1 Solution
Alakananda_BG
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 250 replies posted

Hi @smirnsky ,

As we can see you are using PSOC 61, but in PSOC61 CM0+ core is reserved for system functions and is not available for applications.

If you see the makefile or the linker script there is a dependency for CM0+ core also, because of which you are getting the error mentioned above.

Can you please use PSOC 62 which supports dual core operations.

Regards,

Alakananda

View solution in original post

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3 Replies
Alakananda_BG
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 250 replies posted

Hi @smirnsky ,

As we can see you are using PSOC 61, but in PSOC61 CM0+ core is reserved for system functions and is not available for applications.

If you see the makefile or the linker script there is a dependency for CM0+ core also, because of which you are getting the error mentioned above.

Can you please use PSOC 62 which supports dual core operations.

Regards,

Alakananda
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smirnsky
Level 1
Level 1
5 sign-ins First reply posted First question asked

hi @Alakananda_BG,  thank you for your reply

i erased the code that allocates cmo+ memory from the app0 and app1ld files.

and i even succeeded in uploading the bootloader code to the device.

my new problem is that uploading the app code to the device using the dfu host tool does not work....

the blinky example code is uploaded normally, but I don't know why the application code isn't uploading.

So I tried debugging.

an error occurs when trying to write to the sflash_user_data area.

 -> I wanted to upload only the app1 code. so I made the splash as Noload, but it didn't build.

   --> error :  cy_rtoc_part2 space allocated, but no data. Check .ld file

is there anything else to modify excepts the ld file and makefile?

and is there an option related to the elf file in the modus tool?

====================================================================================

[app1.ld]

/***************************************************************************//**
* \file dfu_cm4_app1.ld
* \version 4.10
*
* The linker file for the GNU C compiler.
* Used for the DFU SDK application 1 firmware project.
* Contains only CM4 sections (no section for the CM0p image that
* starts CM4 application 0). Application 1 is uploaded through
* Bootloader Host Tool using the generated cyadc2 file.
*
* \note
* This linker file is generic and handles common use cases. Your project may not
* use each section defined in the linker file and then you may see warnings
* during the build process. Simply comment out or remove the relevant code
* in the linker file.
*
********************************************************************************
* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation. All rights reserved.
*******************************************************************************/

OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)

STACK_SIZE = 0x1000;

/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)

/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
*/
ram_common (rwx) : ORIGIN = 0x08002000, LENGTH = 0x0400

/* Note: the ram_appX_core1 regions has to be 0x400 aligned
* as they contain Interrupt Vector Table Remapped at the start.
*/
ram_app0 (rwx) : ORIGIN = 0x08002400, LENGTH = 0x1D380
ram_app1 (rwx) : ORIGIN = 0x08002400, LENGTH = 0x1D380

flash_app0 (rx) : ORIGIN = 0x10000000, LENGTH = 0x8000
flash_app1 (rwx) : ORIGIN = 0x10008000, LENGTH = 0x64000

flash_boot_meta (rwx) : ORIGIN = 0x1007FC00, LENGTH = 0x400

/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */


/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}

/* The DFU SDK metadata limits */
__cy_boot_metadata_addr = ORIGIN(flash_boot_meta);
__cy_boot_metadata_length = __cy_memory_0_row_size;

/* The Product ID, used by CyMCUElfTool to generate a updating file */
__cy_product_id = 0x01020304;

/* The checksum type used by CyMCUElfTool to generate a updating file */
__cy_checksum_type = 0x00;

/* Used by the DFU SDK application to set the metadata */
__cy_app0_verify_start = ORIGIN(flash_app0);
__cy_app0_verify_length = LENGTH(flash_app0) - __cy_boot_signature_size;
__cy_app1_verify_start = ORIGIN(flash_app1);
__cy_app1_verify_length = LENGTH(flash_app1) - __cy_boot_signature_size;

/*
* The size of the application signature.
* E.g. 4 for CRC-32,
* 32 for SHA256,
* 256 for RSA 2048.
*/
__cy_boot_signature_size = 4;


/*******************************************************************************
* End of CM4 and CM0+ linker script common region
*******************************************************************************/

/*
* DFU SDK specific: aliases regions, so the rest of code does not use
* application specific memory region names
*/
REGION_ALIAS("flash", flash_app1);
REGION_ALIAS("ram", ram_app1);


/* DFU SDK specific: sets an app Id */
__cy_app_id = 1;

/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_START = ORIGIN(flash);

/* DFU SDK specific */
/* CyMCUElfTool uses these ELF symbols to generate an application signature */
__cy_app_verify_start = ORIGIN(flash);
__cy_app_verify_length = LENGTH(flash) - __cy_boot_signature_size;


/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)

/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions flash and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*
* For the DFU SDK, these additional symbols are defined:
* __cy_app_id
* __cy_product_id
* __cy_checksum_type
* __cy_boot_metadata_addr
* __cy_boot_metadata_length
*/


SECTIONS
{
/* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */
.cy_boot_metadata :
{
KEEP(*(.cy_boot_metadata))
} > flash_boot_meta

/* Cortex-M4 application image */
.text FLASH_CM4_START :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;

. = ALIGN(4);
*(.text*)

KEEP(*(.init))
KEEP(*(.fini))

/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)

/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)

/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)

KEEP(*(.eh_frame*))
} > flash


.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash

__exidx_start = .;

.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;


/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;

/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */

/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */

__copy_table_end__ = .;
} > flash


/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash

__etext = . ;


.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram


.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;

*(vtable)
*(.data*)

. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);

. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);


. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);

KEEP(*(.jcr*))
. = ALIGN(4);

KEEP(*(.cy_ramfunc*))
. = ALIGN(4);

__data_end__ = .;

} > ram


/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram


/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram


.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram


/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram

/* DFU SDK specific */
/* The noinit section, used across all the applications */
.cy_boot_noinit (NOLOAD) :
{
KEEP(*(.cy_boot_noinit));
} > ram_common

/* The last byte of the section is used for AppId to be shared between all the applications */
.cy_boot_noinit.appId ORIGIN(ram_common) + LENGTH(ram_common) - 1 (NOLOAD) :
{
KEEP(*(.cy_boot_noinit.appId));
} > ram_common


/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);

/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

/*
* The DFU SDK section for an app verification signature.
* Must be placed at the end of the application.
* In this case, last N bytes of the last flash row inside the application.
*/
.cy_app_signature ABSOLUTE(ORIGIN(flash) + LENGTH(flash) - __cy_boot_signature_size) :
{
KEEP(*(.cy_app_signature))
} > flash = 0


/* Emulated EEPROM flash area */
.cy_em_eeprom (NOLOAD):
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom


/* Supervisory flash: User data */
.cy_sflash_user_data (NOLOAD):
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data


/* Supervisory flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar (NOLOAD):
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar


/* Supervisory flash: Public Key */
.cy_sflash_public_key (NOLOAD):
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key


/* Supervisory flash: Table of Content # 2 */
.cy_toc_part2 (NOLOAD):
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2


/* Supervisory flash: Table of Content # 2 Copy */
.cy_rtoc_part2 (NOLOAD):
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2


/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip (NOLOAD):
{
KEEP(*(.cy_xip))
} > xip


/* eFuse */
.cy_efuse (NOLOAD):
{
KEEP(*(.cy_efuse))
} > efuse


/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}


/* The following symbols used by the cymcuelftool. */
/* flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00080000;
__cy_memory_0_row_size = 0x200;

/* Emulated EEPROM flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;

/* Supervisory flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;

/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;

/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;

/* EOF */

====================================================================================

thank you!

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smirnsky
Level 1
Level 1
5 sign-ins First reply posted First question asked

when a write request was made to a memory area other than the application1 memory area, it was forcibly return PASS and it downloaded successfully.

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