PSoC™ 6 Forum Discussions
Hello,
For the project that we are working on we are using the TRNG inside the CY8C6347 to generate some values (AES initialization vectors for example) on a somewhat regular basis and want to make sure that the numbers that are generated are valid.
In reading the TRM it describes two "health monitor" capabilities that are built into the hardware, however looking at the PDL implementation it does not appear that this functionality is being enabled. Is there a reason for not having this enabled? If we were to implement our own code based on `Cy_Crypto_Core_V1_Trng()` are there any suggested starting points for the counters and window size to use for the health checks?
Also on a related note the PDL is enabling/disabling the TRNG for each operation. I'm guessing this is to help reduce power consumption as the TRM indicates that the ring buffers that make up TRNG "consume a significant amount of power" but there is no value in the datasheet indicating how much power the TRNG consumes. Is there a nominal power consumption value that we can use to determine if it is better for us to be enabling/disabling the TRNG for each 32-bit value or if it would be better to generate multiple 32-byte values in succession without disabling the TRNG after each one.
Thanks,
Nate
Show LessHi I'm working with the EVK: CY8CKIT-064S0S2-4343W
I'm using Modustoolbox 3.0 I've started a new application from example UART_Transmit_and_Receive for CY8CKIT-064B0S2-4343W and migrated it for CY8CKIT-064S0S2-4343W using this guide:
https://community.infineon.com/t5/PSoC-6/How-to-run-examples-of-peripheral-on-CY8CKIT-064S0S2-4343W/m-p/356686
I've compiled the project successfully
I've programmed the PSOC and this is the log:
Open On-Chip Debugger 0.11.0+dev-4.4.0.2134 (2022-09-08-13:07)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
kitprog3 set_latest_version: X:/Infineon/Tools/ModusToolbox/tools_3.0/fw-loader 2.40.1241
** Main Flash size limited to 0x1D0000 bytes
adapter speed: 2000 kHz
adapter srst delay: 0
adapter srst pulse_width: 5
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
** Using POWERUP_DELAY: 5000 ms
** Using TARGET_AP: cm4_ap
** Using ACQUIRE_TIMEOUT: 15000 ms
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
Info : Using CMSIS-flash algorithms 'CY8C6xxA_SMIF_S25FL512S' for bank 'psoc64_smif_cm4' (footprint 12780 bytes)
Info : CMSIS-flash: ELF path: ../flm/cypress/cat1a/CY8C6xxA_SMIF_S25FL512S.FLM
Info : CMSIS-flash: Address range: 0x18000000-0x1BFFFFFF
Info : CMSIS-flash: Program page size: 0x00001000 bytes
Info : CMSIS-flash: Erase sector size: 0x00040000 bytes, unified
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : Using CMSIS-DAPv2 interface with VID:PID=0x04b4:0xf155, serial=160C19A4002A9400
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.40.1241
Info : KitProg3: Pipelined transfers enabled
Info : KitProg3: Asynchronous USB transfers enabled
Info : VTarget = 3.319 V
Info : kitprog3: acquiring the device (mode: reset)...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x6ba02477
***************************************
** Use overriden Main Flash size, kb: 1856
** Silicon: 0xE4A0, Family: 0x102, Rev.: 0x12 (A1)
** Detected Device: CYS0644ABZI-S2D44
** Flash Boot version: 4.0.1.1089
** SFlash version: 0x4bbb0
***************************************
Info : gdb port disabled
Info : starting gdb server for psoc64.cpu.cm4 on 3333
Info : Listening on port 3333 for gdb connections
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
Info : SWD DPIDR 0x6ba02477
Info : kitprog3: acquiring the device (mode: reset)...
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Info : Waiting up to 15.0 sec for the handshake from the target...
Info : [psoc64.cpu.cm4] external reset detected
psoc64.cpu.cm4 halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x1600400c msp: 00000000
** Programming Started **
auto erase enabled
Info : Flash write discontinued at 0x1002cf53, next section at 0x10050000
Info : Padding image section 0 at 0x1002cf53 with 173 bytes (bank write end alignment)
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Info : Padding image section 1 at 0x100591f2 with 14 bytes (bank write end alignment)
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wrote 221696 bytes from file X:/mtw/UART_Transmit_and_Receive/build/CY8CKIT-064S0S2-4343W/Debug/mtb-example-psoc6-uart-transmit-receive.hex in 3.124608s (69.289 KiB/s)
** Programming Finished **
** Program operation completed successfully **
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Info : SWD DPIDR 0x6ba02477
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Info : [psoc64.cpu.cm4] external reset detected
shutdown command invoked
Info : psoc64.dap: powering down debug domain...
1. I don't understand what this error means: Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
2. After programming I'm observing the COM port of the KitProg and what I see is this:
[INF] /******************************************************/
[INF] PSoC6 CyBootloader Application 1.1.0.1796
[INF] /******************************************************/
[INF]
[INF] CypressBootloader Started
[INF] Secondary Slot 2 will upgrade from External Memory
[INF] Enabled multi-image N = 2:
[INF] External Memory initialized w/ SFDP.
[INF] Swap type: none
[INF] Swap type: none
[ERR] Image in the primary slot is not valid!
[INF] CypressBootloader found none of bootable images
[ERR] There is an error occurred during bootloader flow. MCU stopped.
Why the MCU doesn't boot from the primary slot?
Why the MCU secondary slot is not erased? What is this program?
Thanks
Michael H.
Show LessHi!
I work on my MTB projects in VS code. I am able to use an instance of modus shell separate from my vs code instance containing my project.
Instead, I would like vs code to know the path to modus shell. I naively added the path to my settings.json file, which is the configuration file, as such:
"terminal.integrated.profiles.windows": {
"Modus": {
"path": "C:\\Users\\jcbsk\\AppData\\Roaming\\Microsoft\\Windows\\Start Menu\\Programs\\ModusToolbox 2.2\\modus-shell 1.1.0.lnk"
}
},
But this causes an error:
The terminal process failed to launch: A native exception occurred during launch (Cannot create process, error code: 193).
Any way I can achieve my goal? Thanks!
Show LessHello,
I am using cy8c6136.
I am using the modified basic DFU bootloader project by me.
I write the bootloader.hex file into the blank state MCU and dfus APP1 using dfuh-tool.
There’s no problem here.
But, in a specific situation (button input and using enterDFU() ) in APP1, the bootloader does not run.
APP1 seems to be executed immediately without going through bootloader.
The reason is that there is no port output(about 5 Sec) in the bootloader main() inserted by me.
APP1 is an IAR project, and the *.icf file has been modified.
I attach the bootloader project and APP1 config file.
The common_ram part is for determining whether the bootloader proceeds DFU.
#define BOOTLOADER_ID (0u) // App ID of bootloader
void enterDFU(void)
{
dbg("DFU mode start!!!");
common_ram->validMark = COMMON_RAM_VALIDT_MARK;
common_ram->dfuMark = DFU_START_MARK;
common_ram->dfuState = 0;
common_ram->dfuStatus = 0;
Cy_DFU_ExecuteApp(BOOTLOADER_ID);
// CySoftwareReset();
}
Additionally, I wonder why the ram_common area and the .noinit area are different after build.
/* The noinit section, used across all the applications */
.cy_boot_noinit (NOLOAD) :
{
KEEP(*(.cy_boot_noinit));
} > ram_common
I would like some help on which part is the problem.
Thank you.
Show LessHi I'm working with the EVK: CY8CKIT-064S0S2-4343W
I'm using Modustoolbox 3.0 I've started a new application from example UART_Transmit_and_Receive for CY8CKIT-064B0S2-4343W and migrated it for CY8CKIT-064S0S2-4343W using this guide:
https://community.infineon.com/t5/PSoC-6/How-to-run-examples-of-peripheral-on-CY8CKIT-064S0S2-4343W/...
I've compiled the project successfully
I've programmed the PSOC and this is the log:
Open On-Chip Debugger 0.11.0+dev-4.4.0.2134 (2022-09-08-13:07)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
kitprog3 set_latest_version: X:/Infineon/Tools/ModusToolbox/tools_3.0/fw-loader 2.40.1241
** Main Flash size limited to 0x1D0000 bytes
adapter speed: 2000 kHz
adapter srst delay: 0
adapter srst pulse_width: 5
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
** Using POWERUP_DELAY: 5000 ms
** Using TARGET_AP: cm4_ap
** Using ACQUIRE_TIMEOUT: 15000 ms
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
Info : Using CMSIS-flash algorithms 'CY8C6xxA_SMIF_S25FL512S' for bank 'psoc64_smif_cm4' (footprint 12780 bytes)
Info : CMSIS-flash: ELF path: ../flm/cypress/cat1a/CY8C6xxA_SMIF_S25FL512S.FLM
Info : CMSIS-flash: Address range: 0x18000000-0x1BFFFFFF
Info : CMSIS-flash: Program page size: 0x00001000 bytes
Info : CMSIS-flash: Erase sector size: 0x00040000 bytes, unified
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : Using CMSIS-DAPv2 interface with VID:PID=0x04b4:0xf155, serial=160C19A4002A9400
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.40.1241
Info : KitProg3: Pipelined transfers enabled
Info : KitProg3: Asynchronous USB transfers enabled
Info : VTarget = 3.319 V
Info : kitprog3: acquiring the device (mode: reset)...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x6ba02477
***************************************
** Use overriden Main Flash size, kb: 1856
** Silicon: 0xE4A0, Family: 0x102, Rev.: 0x12 (A1)
** Detected Device: CYS0644ABZI-S2D44
** Flash Boot version: 4.0.1.1089
** SFlash version: 0x4bbb0
***************************************
Info : gdb port disabled
Info : starting gdb server for psoc64.cpu.cm4 on 3333
Info : Listening on port 3333 for gdb connections
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
Info : SWD DPIDR 0x6ba02477
Info : kitprog3: acquiring the device (mode: reset)...
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Info : Waiting up to 15.0 sec for the handshake from the target...
Info : [psoc64.cpu.cm4] external reset detected
psoc64.cpu.cm4 halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x1600400c msp: 00000000
** Programming Started **
auto erase enabled
Info : Flash write discontinued at 0x1002cf53, next section at 0x10050000
Info : Padding image section 0 at 0x1002cf53 with 173 bytes (bank write end alignment)
[ 33%] [########## ] [ Erasing ]
[ 35%] [########### ] [ Erasing ]
[ 40%] [############ ] [ Erasing ]
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Info : Padding image section 1 at 0x100591f2 with 14 bytes (bank write end alignment)
[100%] [################################] [ Erasing ]
[ 79%] [######################### ] [ Programming ]
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wrote 221696 bytes from file X:/mtw/UART_Transmit_and_Receive/build/CY8CKIT-064S0S2-4343W/Debug/mtb-example-psoc6-uart-transmit-receive.hex in 3.124608s (69.289 KiB/s)
** Programming Finished **
** Program operation completed successfully **
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Info : SWD DPIDR 0x6ba02477
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Info : [psoc64.cpu.cm4] external reset detected
shutdown command invoked
Info : psoc64.dap: powering down debug domain...
1. I don't understand what this error means: Error: [psoc64.cpu.cm4] Target not examined, will not halt after reset!
2. After programming I'm observing the COM port of the KitProg and what I see is this:
[INF] /******************************************************/
[INF] PSoC6 CyBootloader Application 1.1.0.1796
[INF] /******************************************************/
[INF]
[INF] CypressBootloader Started
[INF] Secondary Slot 2 will upgrade from External Memory
[INF] Enabled multi-image N = 2:
[INF] External Memory initialized w/ SFDP.
[INF] Swap type: none
[INF] Swap type: none
[ERR] Image in the primary slot is not valid!
[INF] CypressBootloader found none of bootable images
[ERR] There is an error occurred during bootloader flow. MCU stopped.
Why the MCU doesn't boot from the primary slot?
Why the MCU secondary slot is not erased? What is this program?
Thanks
Michael H.
Show Lessthe emwin spport the GUIDRV_LIN driver
I use GPIO to make it ,the code like this:
#define LCD_CLR_A0() cyhal_gpio_write(pins->spi_dc, false)
#define LCD_SET_A0() cyhal_gpio_write(pins->spi_dc, true)
#define LCD_CLR_CLK() cyhal_gpio_write(pins->spi_sclk, false)
#define LCD_SET_CLK() cyhal_gpio_write(pins->spi_sclk, true)
#define LCD_CLR_DATA() cyhal_gpio_write(pins->spi_mosi, false)
#define LCD_SET_DATA() cyhal_gpio_write(pins->spi_mosi, true)
#define LCD_CLR_CS() cyhal_gpio_write(pins->spi_cs, false);
#define LCD_SET_CS() cyhal_gpio_write(pins->spi_cs, true);
/* Write 1 byte, MSB first */
void Send1(unsigned char Data) {
if ((Data >> 7) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
if ((Data >> 6) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
if ((Data >> 5) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
if ((Data >> 4) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
if ((Data >> 3) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
if ((Data >> 2) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
if ((Data >> 1) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
if ((Data >> 0) & 1) LCD_SET_DATA(); else LCD_CLR_DATA(); LCD_CLR_CLK(); LCD_SET_CLK();
}
but the frequency is just 1MHZ,the signal request almost 48Mhz, clock of CM4 is 100Mhz and the Peripherals clock drivers set 1, so the Peripherals clock can up to 50Mhz . but when build this project ,there are some mistaks like this :
so how to make the frequency up to 48Mhz ,and make this mistaks dis.
Show LessHello Community,
I am observing a strange build problem with MCUBoot Roll back code example with ModusToolbox 2.4;
I initially tried this example on MTB2.3.1 and everything works perfectly fine. But, when I started using this CE in MTB2.4, it throws a strange linker error.
"arm-none-gnueabi/bin/ld.exe: Cannot find : Invalid Arugument"
Collect.exe: error: ld returned 1 exit status
Is this a known issue or something is wrong with my build setup ?
Thanks in Advance,
Stephan C
Show LessHi,
from Cypress's SEGGER emWin graphics library 6.26.0 Quick Start guide, it mentions
This section provides the step-by-step instructions how to implement a simple "Hello World" application using emWin.
- Add emWin to the project. For ModusToolbox™, add emWin to the project using the Middleware selector.
1. Now, my question is 2-fold because I don't know how to do either of the options in step 1. I want to work with vscode, so Ideally I would like to add a middleware library without having to open the eclipse IDE for MTB. Is there a way to do that?
2. but also, I don't even know how to add the emWin middleware to a project in eclipse MTB. I just created a Hello world application, and I tried right clicking on the project name to add middleware but it doesn't seem to be the right way because it is not there:
How can I add the emWin library to any given project in eclipse MTB?
3. I have a third extra question, just for understanding. Does the mtb_shared folder contain everything in advance, or it grows as you add middleware to the projects in your current workspace. I guess my question is, if you have a git repo with a MTB project, should you include mtb_shared with it, or it always contains standard files and is going to be provided by the MTB software and no need to clone it into the repository?
Show Less
I'm using the CY8C6244AZI-S4D93.
Device Configurator 4.0 generate TCPWM related code with TCPWM_ver2.
But, Cy_TCPWM_Enable_Multiple() & Cy_TCPWM_TriggerStart () support only TCPWM_ver1.
Please advise me, Which one can support TCPWM_ver2 as the above functions?
Thanks for reading.
Show LessDear All,
I am using cyBLE-416045-02 BLE controller on my custom PCB. I connected MOSI and MISO pins to 9.0 and 9.1 on controller (scb2 block). and SCLK and CS pin to 5.2 and 5.3 on controller (scb5 block). Now I cannot use my spi pins since it connected to different scb. Is there any way to configure this in software side. Please help.