PSoC™ 6

Hi,

We are trying to port the existing firmware in PSOC Creator to ModusToolbox to make it available for the new chips.

However, the biggest challenge we are facing right now is the Analog Multiplexer that's not available in ModusToolbox as it is in PSOC Creator.

I'm wondering if there is any example on how to use the AMUX in ModusToolbox?

Any help will be much appreciated.

Thanks in advance.

GP

I would like to confirm my observation when calling the Cy_Crypto_Core_ECC_SignHash() and Cy_Crypto_Core_ECC_MakeKeyPair() functions.  The Cy_Crypto_Core_ECC_MakeKeyPair() returns the public key (X & Y) in little endian format, same for the signature (R & S) returned by the Cy_Crypto_Core_ECC_SignHash() function.  I verified this by using Mbedtls to generate the public key from a private key created by Cy_Crypto_Core_ECC_MakeKeyPair().

Hello,

I have questions about Flash and Emulated EEPROM.

1. The flash endurance is described in the datasheet as 100k cycles.
Does each row of flash individually have 100k cycle endurance?

2. I'm using the Emulate_EEPROM example in modus toolbox. (CY8CKIT-062-WIFI-BT)
Please let me know how it works internally when using Em_EEPROM.

I want to know about the case of repeatedly writing a few bytes of data to the same address.
For example, when only a few bytes are to be written, will the entire line (512 bytes) including this address be erased and re-written?
Does the Em_EEPROM algorithm read the entire existing row of data into RAM before it is deleted, then modify only a few bytes and write it to flash?

Thanks and Regards,
YS

I use PSOC Creator 4.4 and in the display section I did not find the normal LCD, I have found Graphical only.

i debug the program, the program  enters the Cy_Syslib_ProcessingFault function.   

when the program  runs to the

, The program will sure enter cy_ Syslib_ Processingfault function.

When I use a certain value instead of uitemp0, the program will not enter the fault function.

what's the reason? Thanks!

Hello,

I'm investigating  either PSoC64 family is certified FIPS 140-3 or not.

If not, please tell me type of other certified FIPS .

Please check and answer this.

Best regards,

Yuki Aikawa

Hello, I have a question about the problem that occurred while creating the file 'bin' in 'Keil'.

; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
    ER_FLASH_VECTORS +0
    {
        * (RESET, +FIRST)
    }

    ER_FLASH_CODE +0 FIXED
    {
        * (InRoot$$Sections)
        * (+RO)
    }

    ER_RAM_VECTORS RAM_START UNINIT
    {
        * (RESET_RAM, +FIRST)
    }

    RW_RAM_DATA +0
    {
        * (.cy_ramfunc)
        * (+RW, +ZI)
    }

    ; Place variables in the section that should not be initialized during the
    ; device startup.
    RW_IRAM1 +0 UNINIT
    {
        * (.noinit)
    }

    ; Application heap area (HEAP)
    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
    { 
    }

    ; Stack region growing down
    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
    {
    }

    ; Used for the digital signature of the secure application and the
    ; Bootloader SDK application. The size of the section depends on the required
    ; data size.
    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
    {
        * (.cy_app_signature)
    }
}

; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
    .cy_em_eeprom +0
    {
        * (.cy_em_eeprom)
    }
}

Above is the contents of the 'sct' file in the ToolChain_ARM folder.

If you proceed with the build in the current situation, it will be displayed as a folder, not a file, as shown below.

If i use 'hex2bin' to switch to 'bin', the function "EM_EEPROM" will not be available.

If you look at the 'sct' code above, it seems to be caused by the load area being divided into LR_EM_EEPROM and LR_IROM1.

I want to know how to combine the areas of "LR_EM_EEPROM" and "LR_IROM1" to build.

Hello,

I'm investigating ECC support for internal Flash / SRAM in the PSoC64 family.

I found the below link.
https://community.infineon.com/t5/PSoC-6/Does-PSoC6-support-Error-Correcting-Code-for-memory/m-p/216379#M8011

Ans: PSoC 6 BLE devices do not support ECC on either Flash or SRAM.

Does PSoC 64 family also not support ECC either Flash or SRAM?

Best Regards,

Naoaki Morimoto

Device is CYBLE-416045-02, sometimes two consecutive I2C transactions fail. Happens with (Write then read)  and (Write then Write) cases. 

Pseudo code:

cy_stc_scb_i2c_master_xfer_config_t transfer;
uint8_t writeBuffer[1UL] = { subAddress };
transfer.slaveAddress = i2cAddress;
transfer.buffer       = writeBuffer;
transfer.bufferSize   = 1;
transfer.xferPending  = true; /* Do not generate Stop 
Cy_SCB_I2C_MasterWrite(SCB1, &transfer, context);
xSemaphoreTake(i2c_sem);// wait for CY_SCB_I2C_MASTER_WR_CMPLT_EVENT callback
Cy_SCB_I2C_MasterRead(); //returns CY_SCB_I2C_MASTER_NOT_READY

If CMPLT_EVENT was received, how can a master not be ready ?

I found if I wait 20uS after a MASTER_NOT_READY, it works. But I cannot explain why I need to waste that time.