PSoC™ 6 Forum Discussions
I am trying to integrate three things into one project, ADC, PWM and USB CDC. the ADC and PWM work well together, but when I try to add the USB CDC to it, the USB CDC won't start.
So I need it ADC and PWM to work, the USB CDC receives some data from the user and displays it back using the ADC value of the pin. But USB CDC is not working properly at USBD_Start() . I have attached the code for reference.
I am using CY8CKIT-062S2-43012 for this purpose. And am also using another BSP CY8C6245LQI-S3D72. So I'm hoping it will work for both.
I have attached an image of the program stuck in the cy_syslib file. Please refer to it as well.
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/PSoC-6/%E5%B0%86-USB-CDC-ADC-%E5%92%8C-PWM-%E9%9B%86%E6%88%90%E5%88%B0%E5%8D%95%E4%B8%AA%E9%A1%B9%E7%9B%AE%E4%B8%AD-USBD-Start-%E4%BC%9A%E5%A4%B1%E8%B4%A5/td-p/463199
Show LessHi all Currently I am working on a project where I have to read ~2000 bytes from SPI so is there any way to extend RX FIFO of the SCB block?
Hi,
I was reading the Architecture Technical Manual, and on page 38 it is mentioned that "The CPUSS has up to three identical SRAM controllers; see the device datasheet for details." I tried to find clear information about the "three" SRAM controllers on the device datasheet but I couldn't clarify this question:
Is the SRAM a one block memory or a 3 block separate memory with each block having its own controller and connection to the system bus? To give a little more color on my question, I was wondering if the SRAM will suffer from contention delays if both cores are accessing simultaneously this memory.
Thanks.
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i've been succesfull with creating custom libraries and creating a project that uses the PDL to toggle an LED to a digital pin on the Arduino header?
Can you create your own Library in ModusToolbox?
Now I am attempting to combine this knowledge to Create a libray that implements the Arduino digital pin calls .
I have a cutom library project called arduino., that I created using the steps that I did to create a custom library.the 2 files gpio.c and gpio.h have the 2 functions impleenting the arduino calls:
- digitalWrite(LED, HIGH/LOW); // set the pin HIGH OR LOW
- delay(500); // for 500ms
I'm stuck at implementing the PDL api into my custom library?
I don't see anyware from the IDE to run the Device configurator to select the BSP and the Libraries for this project.?
Is this the way to implement the PDL calls in a reusable library? or is there a better way?
The screen shot below shows MTD with the Project, gpio.c and the error that I would expect to receive.
Any thoughts on what I might be missing out on?
Regards
Steve K
screenshotbelow
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Hello PSOC6 Forum,
I am working to add the DFU functionality to my application and I'm using the CE213903 sample project as a working reference. I have integrated my core application with the working sample project and I am able to successfully update app1 into the main flash using app0.
App1 is transferred over to app0 with a python program that I wrote that places the .cyacd2 data into the DFU protocol over UART. This is working well as I have been able to successfully transfer the CE213903 project with my program.
The issue is when app0 tries to verify app1, the function Cy_DFU_GetAppMetadata(appId, &appVerifyStartAddress, &appVerifySize); called in the function Cy_DFU_ValidateApp() found in cy_dfu.c doesn't return the correct start address of app1 or the size. I get 0x00000000 for the address. Naturally, the app doesn't execute since app0 can't verify app1.
When I do a memory dump after app1 is loaded, I can see the application data at the correct address as defined in the dfu_cm0p.ld & dfu_cm4.ld files for both cores. I can also see the checksum at the end of the definition for app1 core 1 which is what the Cy_DFU_GetAppMetadata() is looking for. Running my update program several times gives the same checksum at this location, so I'm assuming the data transfer is correct and repeatable.
I get the feeling that the metadata that specifies the app start address and size didn't get set somewhere when the DFU is running or it put the value in some other location.
Also, I should mention that I have modified both dfu_cm0p.ld & dfu_cm4.ld files in both application as instructed in the CE213903 instructions. I took a step further gave some more space between core0 and core1 so that the linker wouldn't accidentally over write past the starting address of the second core (if that is possible).
Any help would be greatly appreciated. I'm using PSOC creator and my target chip is the CY8C6247FDI-D32. I've attached the .ld files for app1. They are identical as the files for app0 except for the part where app1 is defined.
Show LessI am using the MCUBoot multiproject (cm0p + cm4) solution. How can I copy the app_combined.hex using a post-build makefile command.
If I put the post-build command in the makefile of the cm4 project, it copies the older app_combined.hex (because the combined file is generated after the cm4 build is completed).
Thanks.
Show LessHow can I modify only a specified section of Flash during development?
I would like to be able to program a 2nd firmware image in a location offset from an existing firmware image on a PSoC 61 such that I can test modifications to the 2nd firmware without affecting the first.
Greg
Show LessWhat serial interface examples exist that support communication to the TFT driver, Sitronix ST7789V on CY8CKIT-028-TFT which is used on CY8CKIT-062-WiFi-BT?
Sitronix ST7789V uses similar interfaces to Ilitek Ili9163C which is found on DisplayTech DT018ATFT. The parallel interfaces to these TFTs is rather straightforward. For applications that are pin limited yet don’t need the full bandwidth, a serial interface is preferred.
These serial interfaces are NOT standard. The serial interfaces are marked as SPI on the Display and Display Driver datasheets. However, they appear to be custom:
- 3-line Serial Interface: CSX, SDA, SCL
- 4-line Serial Interface: CSX, D/CX, SDA, SCL
The 3-pins serial use: CSX (chip enable), SCL(serial clock) and SDA(serial data input/output) and the 4-pins serial use: CSX(chip enable), D/CX(data/ command select), SCL(serial clock), and SDA(serial data input/output).
Note: There’s a caveat when using 3-pin interface that a 9-bit packet is used to support the D/CX function.
Note: It is interesting that that Display and Driver datasheets note the DB0 pin is also an SDA. It doesn’t specifically state, but I wonder if that 2nd SDA could be used to support Full-Duplex mode.??? If it could, a standard SPI driver might work.
Standard SPI supports full-duplex with clock, two data lines and Chip Select. There is a 3-wire version (aka National’s Microwire) of SPI, which uses half-duplex, single data line for transmit and receive.
- SPI signals: SCLK, MOSI, MISO, CS
- 3-wire SPI signals: SCLK, SISO, CS
ModusToolbox’s Device Configurator has an option for “National Semiconductor (Microwire)” when configuring a Serial Interface. It doesn’t appear to support the 9-bit packet that has the preceding D/CX bit.
I’d prefer NOT to bit bang the interface.
Show LessHello,
I have a project on PSoC 3 (CY8C3246PVI-147) that I would like to transport to PSoC 6 (CY8C6347BZI-BLD43), however, in the TopDesign of the project for PSoC 6 some components appear to be incompatible and I cannot find their counterparts in the component catalog. How can this be solved?
Thank you very much
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