PSoC™ 6 Forum Discussions

Hi,

I've been having some trouble with a UDB design which I have just tracked down to an accumulator register write which is failing sometimes.

The design uses 8 UDB's, but the datapath in question is a simple 8bit stand alone function (not concatenated).

Both cores run at 98MHz, and clk_peri = 98MHz, The bus clock to the UDB's is clk_peri/2 (49MHz) and the datapaths are running at clk_peri/8 (circa 12.5MHz).

I'm writing and reading A0 using CY_SET_REG8() and CY_GET_REG8(), but am finding that writes appear to be failing a bit less than 50% of the time. The writes are coming from CoreM0.

Is there a need to synchronise writes to the accumulator registers? Any other reason why writes periodically fail?

Timing in the design is reported as being met.

Thanks in advance for any pointers.

Charles

Hi all:

    About the manufacturer specific data of the Advertisement Packet,the company  is showed which must be the member of bluetooth SIG?

Hello there,

I was hoping to get my footprint reviewed with the modifications I made (removal of various pads of GPIO's we aren't using). I have had success before with similar modifications but prefer to have it verified by you guys now. I know it's far from ideal but this is just to get us by until we can get our hands on the QFN package later this year. So the question, do these pad removals make it extremely unstable? (Both mechanically and electrically).

Thank you guys

Hi there,

We have a sensor bus manager where we are pulling data from multiple sensors at a time. Is it possible to to do this while the system is in deep sleep/sleep mode? We should note that we are pulling data and have Bluetooth configured to a single core.

Previously, in psoc 4 the i2c could only operate while the core in in sleep mode. Is this the same for psoc 6?

Best,

Steve

Hello,

There are three type of register for controlling protection context.

They are MPUx_MS_CTL.PC, SMPU_MSx_CTL.PC_MASK_15_TO_1 and SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1.

1) MPUx_MS_CTL.PC

I think this register select protection context of a master which is assigned by each register. That is, Master work as protection context # indicated by PC.

If MPU0_MS_CTL.PC is 3, a program on CM0+ work as protection context 3. If CM0+ try to access an area except protection context 3. the area of protection context 3 is set by SMPU_STRUCTURE_ADDRx register.

2) SMPU_MSx_CTL.PC_MASK_15_TO_1

I think this register select SMPU Structure assigned by protection context of SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1 which SMPU can control.

3) SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1

I think this register indicate each SMPU Structure of protection context which is set by PC_MASK_15_TO_1

If my understanding is wrong, please correct it

Best regards,

Hi.

I am studying PSoC6 with PSoC Creator.

In the datasheet of Global Signal Reference (GSRef) ,

there is a line which I can not understand

> Error conditions such as XMHz Error and Cache Interrupt

Could someone teach me what XMHz Error means?

asanuma

Hello. Received the PSOC6 Kit with BLE and started some testing after watching the Mouser sponsored webinar last week. The supplied BLE USB stick is able to pair up with the kit without issues and can perform Discovery, etc. As far as we know, the slider bar demo is only for the mobile phones. On this relatively new phone (purchased late summer) which works fine as a phone, fails to pair up with the kit. No issue as noted in connecting via the Windows BLE tool.

What is the issue? With the phone or the app or the kit?

Hi,

So I have a simple application with a  GPIO and an interrupt.

I want the interrupt to trigger on either edge.  So using the GUI I set the pin configuration as an input with a pull up, and the input pin to trigger on either edge.  Then I connected the HW connection as shown above and configured the interrupt schematic component using the GUI for auto-select.

So, after building and testing, the interrupt is only triggering on rising edge....

Am I setting this up correctly?

Thanks

Scott