Hey,
I'm trying to build a project which is based on a modified "Security Example" Project.
I want to use the btstack, so deleted the CM0+ project a...
Show More
Hey,
I'm trying to build a project which is based on a modified "Security Example" Project.
I want to use the btstack, so deleted the CM0+ project and modified the linker file to:
/***************************************************************************/
/**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.91
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = 0x1000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
/* ram_cm0p (rwx) : ORIGIN = ORIGIN_OF_SRAM, LENGTH = CM0P_APP_SRAM_SIZE */
/* shared_ram (rwx) : ORIGIN = SHARED_SRAM_START, LENGTH = SHARED_SRAM_SIZE */
ram (rwx) : ORIGIN = CM4_APP_SRAM_START, LENGTH = CM4_APP_SRAM_SIZE
flash_btldr (rx) : ORIGIN = ORIGIN_OF_FLASH, LENGTH = CM0P_BTLDR_FLASH_SIZE
/* protected_storage (rw) : ORIGIN = PROTECTED_MEM_START, LENGTH = PROT_STRG_SIZE */
/* flash_cm0p (rx) : ORIGIN = CM0P_APP_FLASH_START, LENGTH = CM0P_APP_FLASH_SIZE */
/* flash (rx) : ORIGIN = 0x10000000 + CM0P_BTLDR_FLASH_SIZE, LENGTH = MCUBOOT_SLOT_SIZE */
flash (rx) : ORIGIN = 0x10000000 + CM0P_APP_FLASH_SIZE, LENGTH = MCUBOOT_SLOT_SIZE
flash_secondary (rx) : ORIGIN = SECONDARY_SLOT_FLASH_START, LENGTH = MCUBOOT_SLOT_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x20000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* The Product ID, used by CyMCUElfTool to generate a updating file */
__cy_product_id = 0x01020304;
/* The checksum type used by CyMCUElfTool to generate a updating file */
__cy_checksum_type = 0x00;
/* DFU SDK specific: sets an app Id */
__cy_app_id = 0;
/* Used by the DFU SDK application to set the metadata */
__cy_app0_verify_start = ORIGIN(flash);
__cy_app0_verify_length = MCUBOOT_SLOT_SIZE;
__cy_app1_verify_start = ORIGIN(flash_secondary);
__cy_app1_verify_length = MCUBOOT_SLOT_SIZE;
/*******************************************************************************
* End of CM4 and CM0+ linker script common region
*******************************************************************************/
/*
* Aliases regions, so the rest of code does not use
* application specific memory region names
*/
/*REGION_ALIAS("flash", flash_cm4);
REGION_ALIAS("ram", ram_cm4);*/
__cy_app_verify_start = ORIGIN(flash);
__cy_app_verify_length = MCUBOOT_SLOT_SIZE;
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
/* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START + MCUBOOT_HEADER_SIZE :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
/* Cortex-M4 application image */
.text FLASH_CM4_START :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
/* Used for the digital signature of the secure application and the Bootloader SDK application.
* The size of the section depends on the required data size. */
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
{
KEEP(*(.cy_app_signature))
} > flash
/* Protected Storage area */
/* .cy_prot_storage :
{
KEEP(*(.cy_prot_storage))
} > protected_storage*/
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* .shared_ram (NOLOAD):
{
. = ALIGN(4);
__shared_ram_start__ = .;
KEEP(*(.shared_ram))
. = ALIGN(4);
__shared_ram_end__ = .;
} > shared_ram
.cy_sharedmem ORIGIN(shared_ram) + LENGTH(shared_ram) - IPC_SYSTEM_PIPES_SIZE (NOLOAD):
{
. = ALIGN(4);
__public_ram_start__ = .;
KEEP(*(.cy_sharedmem))
. = ALIGN(4);
__public_ram_end__ = .;
} > shared_ram
__SharedSRAMTop = ORIGIN(shared_ram) + LENGTH(shared_ram);
__SharedSRAMLimit = __SharedSRAMTop - SIZEOF(.cy_sharedmem);
/* Check if shared sram overwrites into sram assigned for IPC system pipes */
/* ASSERT(__shared_ram_end__ <= __SharedSRAMLimit, "region shared RAM overflows into system IPC pipes sram region")*/
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
cy_xip :
{
__cy_xip_start = .;
KEEP(*(.cy_xip))
__cy_xip_end = .;
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */
I get a programmable .hex file with this and I can successfully program it to the First Slot of MCUBoot. But MCUBoot then starts into a Bootloop:
INF] MCUboot Bootloader Started (CPU: CM0+) Apr 27 2023 11:54:45
[INF] Device lifecycle=0x01, dead0=0x00, dead1=0x00, secure0=0x00,
secure1=0x00
[INF] Active PC value: 0x00
[INF] Configuring protection units...
[INF] Protection units configured successfully!
[INF] Active PC value after protection unit configuration: 0x01
[INF] boot_swap_type_multi: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[INF] boot_swap_type_multi: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[INF] Swap type: none
[INF] User Application validated successfully
[INF] --- rsp Addr 0x0800FFCC
[INF] --- HDR Addr 0x0800FFCC
[INF] --- br_flash_div_id 0x0000007F
[INF] --- br_image_off 0x00020000
[INF] --- ih_load_addr 0x00000000
[INF] --- ih_img_size 0x0003FB10
[INF] --- ih_hdr_size 0x00000400
[INF] --- ih_protect_tlv_size 0x00000000
[INF] CM0 app stack: 0x08003000
[INF] CM0 app PC: 0x1000012B
[INF] Starting User Application on CM0+. Please wait...
[INF]
=======================================================================
[INF] MCUboot Bootloader Started (CPU: CM0+) Apr 27 2023 11:54:45
[INF] Device lifecycle=0x01, dead0=0x00, dead1=0x00, secure0=0x00,
secure1=0x00
[INF] Active PC value: 0x00
[INF] Configuring protection units...
[INF] Protection units configured successfully!
[INF] Active PC value after protection unit configuration: 0x01
[INF] boot_swap_type_multi: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[INF] boot_swap_type_multi: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[INF] Swap type: none
[INF] User Application validated successfully
[INF] --- rsp Addr 0x0800FFCC
[INF] --- HDR Addr 0x0800FFCC
[INF] --- br_flash_div_id 0x0000007F
[INF] --- br_image_off 0x00020000
[INF] --- ih_load_addr 0x00000000
[INF] --- ih_img_size 0x0003FB10
[INF] --- ih_hdr_size 0x00000400
[INF] --- ih_protect_tlv_size 0x00000000
[INF] CM0 app stack: 0x08003000
[INF] CM0 app PC: 0x1000012B
[INF] Starting User Application on CM0+. Please wait...
[INF]
=======================================================================
[INF] MCUboot Bootloader Started (CPU: CM0+) Apr 27 2023 11:54:45
[INF] Device lifecycle=0x01, dead0=0x00, dead1=0x00, secure0=0x00,
secure1=0x00
The CM4 Application is never called. What am I doing wrong ?
Thank you,
Matthias
Show Less
Aug 24, 2023
Solved
