As we all know, when using the Bluetooth protocol stack, it is not allowed breakpoint debugging, then now PSoC 6 BLE support breakpoint debugging?

I'm making a small project on PSoC 5LP - capacitive sensing controller, mostly for old IBM keyboards (though other capacitive switches should not be much of a problem to support).

Here's the source if anyone is interested: https://github.com/dmaone/CommonSense

Almost got to release and BAM, PSoC6 is announced

I'm not using capsense module - it's just too slow. I use scanning ADC. To make things faster, I drive the short side of the matrix, and scanning long one. Less time spent waiting for the matrix to charge that way.

For beamsprings, that requires 23 ADC inputs.

So, the question is - will PSoC6 support normal AMUX, or it will sport a crippled version with 8 unmovable SARMUX pins, like in PSoC4?

Bluetooth beamspring is a holy grail of mechanical keyboards community, and making a single-chip solution would be awesome (bonus points if the same chip would also supervise battery charging - right now it looks like a separate IC is needed just for that).

As we all know, TI and Nordic have their sniffer, but CY only one Dongle.Dongle can only be made into a BLE Master and can not catch packets,are there plans to do  a BLE sniffer?

Hi there,

Could you let me know please what is the current peak in mA of the BLE peripheral in PSoC6?

When I can have the PSoC6 dev board and according PSoC Creator software to start my experiments?

Does the BLE Stack run on M0+ or M4?

Kind Regards,

Anastasios

Hello,

I have a few questions about two-processor PSoCs.

If I declare a global variable in a header file inside shared-code folder, how will this be compiled?

Will this get compiled as two variables, one for each core? Or will this be compiled as a shared memory location?

If the first, how should I declare shared memory?

And the last question, how will volatile keyword behave in two-processor environment? I used to declare variable as volatile, when it may be accessed from multiple ISRs and/or non-interrupt code. Does this mean that all shared memory should be volatile?

Stanislav

Hi,

What is Smart IO and GPIO_OVT?

Can I connect internal periphery to any pins like at PSoC 5 or some pin are fixed like at PSoC 4?

Thanks.

Hi,

as long as there is no Silicon available, i would like to start some ideas in the PSoC-Creator. I want to be ready at the time, the first samples are available for me.

I use the actual "PSoC Creator  4.0 Update 1 (4.0.0.432)". Is there an addon to implement the features of the PSoC6? Or, ist there anything I'm overlooking?

...hoping to start my first PSoC6 Project.....

Best regards,

Martin Kraus

Hi,

I would like to ask if PSoC6 supports the following.

1. Can we use the PLDs in the Universal Digital Blocks in order to fit a hardware multiplier?
For example, in PSoC4, I could fit a 3x3 bit hardware multiplier using the PLDs. Could we support a 16x16=32bit hardware multiplier in PSoC6's PLDs?

2. Can we access chip's RAM from verilog when we design a custom PSoC6 component?

3. The PSoC4 has the CyBle_SetTxPowerLevel() function to change the transmission power level. The input parameter configures power from -18db to +3db. What are the options in PSoC6? Can we configure the transmission power at -80db for example?

Best Regards,

Yiannis