PSoC™ 6 Forum Discussions
As I understand PSoC 6 will support FreeRTOS. Our product is a wearable and we are interested in sending code via ble to be run as a thread on the CortexM4. This will be in the same spirit to dynamically adding an 'app' to the device which will open new functionality without a complete firmware reflashing.
Is this possible given flash now support non blocking reads/writes and FreeRTOS has the xTaskCreate function which appears to implement dynamic thread creation?
Cypress and Mouser have partnered up to carry out our first PSoC 6 webinar! In this 2-part webinar, Cypress' Alan Hawse (@iotexpert) and Michi Yoneda will walk you through a technical discussion and a series of hands-on lessons focused on enabling you to create next generation, ultra-low-power wireless solutions for the IoT.
The 2-part series will cover:
- The architectural trade-offs between application processors and traditional microcontrollers for IoT applications
- Best practices and needs in today’s and tomorrow’s IoT applications
- Developing next-generation IoT applications with Cypress’ PSoC 6 MCUs with BLE connectivity
- Adding CapSense capacitive-sensing to your next IoT application
Part 1 will take place on September 28th and Part 2 will take place on October 25th, so get registered!
We look forward to discussing and teaching you about our new PSoC 6 MCU!Show Less
Could you provide a function table of PSoC6 60/61/62 family?
Although I refer to doc# 002-18449 Rev.**, I think that table 39 can not confirm all the functions.
So, I want a list of PSoC6 60/61/62 family which is equivalent to PSoC Creator's device selector.Show Less
in the hardware design consideration document page 22 an external NVM is connected to the PSoC and it shows that it is connected to pins P11.7 (clk), P11.2 (cs), P11.6(SI), P11.5 (SO).
When I attempt to connect a SPI device on the PSoC creator on P11 the clk, SI, SO don't go to the same pins in the HW design document.
P11.2 (clk). P11.7 is not enabled for clk on the creator
P11.0 (SI). P11.6 is not enabled for SI on the creator
P11.1 (SO). P11.5 is not enabled for SO on the creator
is that a documentation error and I should follow the PSoC creator?
I thought it may be helpful to any potential PSoC 6 users who may also be new to the PSoC Creator environment to write a 'Hello World!' type tutorial that takes a new user through the tool flow to flash the LED on the board in a couple of different ways. Hopefully, I have simplified navigating through the tools enough that the examples supplied for the PSoC 6 will seem less daunting for new users to get their heads round - speeding up the learning curve a little.
I have posted the tutorial HERE.
I got a CYBLE-022001-00 eval board yesterday and tried to use it standalone (upload code via a Jlink with SWD interface). Create new project with example code, compile with PSoC Creator then export to Eclipse and upload the code via Jlink, everything is OK.
Then I use code from 100 projects in 100 days (#007 broadcaster and peripheral) but this code is not for CYBLE-022001-00 eval board (the pin config for CY8C4247 chip), I forget it and try to upload this code to the board. Although get some errors, the board still run the code (advertise and connect OK) but now I can't connect to the board via Jlink (SWD) anymore (I think the pin config is changed). How can I reset CYBLE-022001-00 eval ?
I just did a nice design with PSoC6! I figured out it would really be small. However, it turns out about the same footprint is necessary for all the external components.
I'm used to have some external components with PSoC3/4/5, no problem. But this time I need at least 25 external capacitors and a fairly large inductor, eating up the same footprint size of the PSoC 6 itself! This is a huge drawback, especially as it's advertised as wearable solution. Also PSoC is know to reduce the BOM.
It's hard to imagine that 2 VDD pins at 0.5mm distance needs 4 additional capacitors! Wat about using resonance free (polymer?) capacitors?
It would really, and I mean REALLY be helpful if you guys at Cypress could provide (component count vs performance) optimized guidelines and (layout) examples. It would be very helpful if the following topics would be covered:
- design examples for several configurations (for example: reduced component digital only, high performance analog, buck/non-buck, BLE/non-BLE, etc)
- capacitor requirements
- use of the buck regulator to power external circuits
- EMI/EFT considerations for PSoC 6