As I understand PSoC 6 will support FreeRTOS. Our product is a wearable and we are interested in sending code via ble to be run as a thread on the CortexM4. This will be in the same spirit to dynamically adding an 'app' to the device which will open new functionality without a complete firmware reflashing.

Is this possible given flash now support non blocking reads/writes and FreeRTOS has the xTaskCreate function which appears to implement dynamic thread creation?

Much Thanks,

Best,

-Nick

I got a CYBLE-022001-00 eval board yesterday and tried  to use it standalone (upload code via a Jlink with SWD interface). Create new project with example code, compile with PSoC Creator then export to Eclipse and upload the code via Jlink, everything is OK.
Then I use code from 100 projects in 100 days (#007 broadcaster and peripheral) but this code is not for CYBLE-022001-00 eval board (the pin config for CY8C4247 chip), I forget it and try to upload this code to the board. Although get some errors, the board still run the code (advertise and connect OK) but now I can't connect to the board via Jlink (SWD) anymore (I think the pin config is changed). How can I reset CYBLE-022001-00 eval ?

Hello,

I just did a nice design with PSoC6! I figured out it would really be small. However, it turns out about the same footprint is necessary for all the external components.

I'm used to have some external components with PSoC3/4/5, no problem. But this time I need at least 25 external capacitors and a fairly large inductor, eating up the same footprint size of the PSoC 6 itself! This is a huge drawback, especially as it's advertised as wearable solution. Also PSoC is know to reduce the BOM.

It's hard to imagine that 2 VDD pins at 0.5mm distance needs 4 additional capacitors! Wat about using resonance free (polymer?) capacitors?

F38 Series | AVX

https://product.tdk.com/info/en/catalog/datasheets/emc_esr_yna15_en.pdf

It would really, and I mean REALLY be helpful if you guys at Cypress could provide (component count vs performance) optimized guidelines and (layout) examples. It would be very helpful if the following topics would be covered:

• design examples for several configurations (for example: reduced component digital only, high performance analog, buck/non-buck, BLE/non-BLE, etc)
• capacitor requirements
• use of the buck regulator to power external circuits
• EMI/EFT considerations for PSoC 6

Thanks!

Rolf