PSoC™ 6 Forum Discussions
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I am using CY8CKIT-059 (PSOC5LP)for AES encryption.
1, I would like to know that PSoC5LP can handle AES hardware encryption? Which device is possible to create the AES hardware encryption?
2. I found CY8CROTO-063 device. Is that correct device to create AES hardware and send the data with BLE?
3. I would like to see the useful link or document or video file of creating the AES hardware in psoc step by step.
Thank you for your time.
PSoC SoftwarePSoC 5LP MCU Community would like to draw a graph for the dac (digital analog converter) value corresponding to each adc (analog digital converter) value that I obtained in my project. ADC (I variable), DAC (J variable) I wrote in the program. I want to plot the graph for the corresponding "j" value for each "I". For chart plotting, I can use nextion or tft display shield board cy8ckit-028-use tft. Can you help with this?
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I am evaluating the PSOC 6 family to replace and existing design using a different micro controller. I need a composite USB CDC device which supports 4 comm ports. The psoc creator supports composite devices, but has insufficient endpoints to support 4 CDC devices. Is there a solution to this? Is the number of endpoints limited by hardware or the USBFS design?
Show LessI'm trying to use CE219517 on CY8CKIT-06-BLE. After building the project I try to programm the Kit.
Then I get the following error measage:
The selected debug target 'CY8C6347BZI-BLD53' is not compatible with the project's selected device 'CY8C5868LTI-LP039'.
I tryed to change the device in the project to CY8C6347FMI-BLD53 and get the following measage:
How to solve the problem?
Thanks
Show LessAfter lots of experience with PSoC 3, 4, 4 BLE, and 5LP, I'm trying to get some experience with the PSoC 6. I'm using the CY8CPROTO-063-BLE prototyping kit with the CYBLE-416045-02 EZ-BLE module on it.
I started with the CE221773 PSoC 6 Hello World example and that ran without any issues. I'm now trying to run the CE212736 Fine Me example, with the LEDs removed (because there's no RGB LED on this kit, and I can use the UART to see what's going on). I'm doing this in PSoC Creator 4.2 with PDL 3.1.0.
If I debug the M0+ core, I can see that it successfully starts the BLE stack and then tries to start the M4 core. If I debug the M4 core, execution never reaches main().
Anybody know what's going on here?
Thanks.
(Project attached even though it's just the Cypress example with the changes mentioned above)@
Show LessI'm getting angry about PSoC6 (CY8C6347BZI-BLD53). I try to perform a Boundary Scan (Goepel) on our prototypes and I only get errors from the insruction and data register. The JTAG signals looks great, the test-byte is shifted out again onto TDO but it looks like the BSDL File is build for the IOSS TAP and not for the CPUSS DAP TAP ???
Does someone have an idea?
Best regards,
Show LessDo we have any guidance on how often the PILO should be trimmed against a high accuracy clock source to maintain a 250ppm accuracy?
This would be for the PSoC 6 module, with the AltHF BLE ECO of 32MHz as the high accuracy clock source.
Do we have any example code to do this as well?
Thanks
Graham
Show LessMy project needs to integrate the PSOC6 Crypto functions with a custom SRAM like interface. When will PSOC Creator fully support the 4343W dev kit? I have been able to create new components targeting PSOC62, but both the programmer and PSOC Creator will not talk to the dev kit. PSOC Creator complains that the device was found but it can not debug it at this time.
From looking at the Modus forum, that tool does not currently support PSOC components. How do I get Verilog components into a 4343W kit? Did I buy the wrong dev kit?
Regards,
Eric
Show LessI am busy with a design where I need to run the CM4 core at 150MHz and also use USB (device). I am using a 12MHz external crystal for the ECO in order to get 48MHz and be below the 0.25% tolerance that USB requires via the PLL. I cannot use the FLL for USB as it has a ~1% tolerance and it can also only go up to 100MHz so cannot reach the 150MHz mark.
I can also use the 8MHz IMO through the PLL and still make the required 0.25% tolerance for USB, but it doe not slve my 150MHz problem
What am I missing?
Regards
Chris
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