PSoC™ 6 Forum Discussions

I'm trying to use CE219517 on CY8CKIT-06-BLE. After building the project I try to programm the Kit.

Then I get the following error measage:

The selected debug target 'CY8C6347BZI-BLD53' is not compatible with the project's selected device 'CY8C5868LTI-LP039'.

I tryed to change the device in the project to CY8C6347FMI-BLD53 and get the following measage:

How to solve the problem?

Thanks

After lots of experience with PSoC 3, 4, 4 BLE, and 5LP, I'm trying to get some experience with the PSoC 6.  I'm using the CY8CPROTO-063-BLE prototyping kit with the CYBLE-416045-02 EZ-BLE module on it.

I started with the CE221773 PSoC 6 Hello World example and that ran without any issues.  I'm now trying to run the CE212736 Fine Me example, with the LEDs removed (because there's no RGB LED on this kit, and I can use the UART to see what's going on).  I'm doing this in PSoC Creator 4.2 with PDL 3.1.0.

If I debug the M0+ core, I can see that it successfully starts the BLE stack and then tries to start the M4 core.  If I debug the M4 core, execution never reaches main().

Anybody know what's going on here?

Thanks.

(Project attached even though it's just the Cypress example with the changes mentioned above)@

Do we have any guidance on how often the PILO should be trimmed against a high accuracy clock source to maintain a 250ppm accuracy?

This would be for the PSoC 6 module, with the AltHF BLE ECO of 32MHz as the high accuracy clock source.

Do we have any example code to do this as well?

Thanks

Graham

I am trying to change the PLL clock using the cypress API functions, instead of the "Clocks" UI section. There is a "walkthrough" here: https://www.cypress.com/file/420571/download on page 132.

My code looks something like this:

int main(void)

{

     uint32_t clkPath = 1;

    Cy_SysClk_ClkPathSetSource(clkPath, CY_SYSCLK_CLKPATH_IN_IMO);

    cy_stc_pll_manual_config_t* config;

    configNew->feedbackDiv = 25UL;

    configNew->referenceDiv = 1UL;

    configNew->outputDiv = 2UL;

    configNew->lfMode = true;

        Cy_SysClk_PllEnable(clkPathManual, 2); //  > 1us delay as suggested on step 3 of TRM   

     Cy_SysClk_PllManualConfigure(clkPath, config);

...

}

It seems that the PLL is already enabled when Cy_SysClk_PllManualConfigure() is called, and i get CY_SYSCLK_INVALID_STATE return code from the function. Any suggestions? Thanks in advance.