PSoC™ 6 Forum Discussions
Hello,
The architecture reference manual for PSoC62 outlines the DP_CTL register in the DAP security section, but the register TRM does not detail this register. Could you please provide the relevant documentation?
The section also describes the ability to enable debug access after authentication. Is this a feature available in PSoC62?
Thanks!
Show LessI've read through various discussions dating back to 2016 that the PSoC6 will eventually support the BLE Mesh standard, given its BLE 5.0 compliant.
When is it likely that the BLE Mesh support will be released for PSoC6 developers to use? Will Cypress be providing an accompanying demo project?
I'm currently using the Flood-Fill Mesh example for the PSoC4 for a current project, but I wish to use the new standard to future-proof my product. Also, I like the fact that the new standards mandates secured/encrypted connections.
Even trying to port the current PSoC4 mesh example to the new BLE Stack of the PSoC6 is causing me significant trouble.
Have also asked this in the PSoC6 Community
Show LessI am new to Cypress microcontrollers and I installed PSoC programmer. I have a custom board with CY8C4125LQI-483 micro on it and I am trying to program it using the 5 pin connector on MiniProg3. The pins on the micro are:
P3[2] for SWD Data
P3[3] for SWD Clk
pin30 for XRES
It says in documentation that the pin assignments on MiniProg3 for SWD protocol are:
SDIO for pin5
SCK for pin4
XRES for pin3
I am totally confused how to connect the 5-pin connector to the micro. So do I connect SDIO to SWD Data and 3.3V external power? Which pin on the 5-pin MiniProg should I use for the GND?
Show LessHello,
I have a SCB configured in SPI mode on PSo62A series and I am wondering if the CS line assertion/deassertion timing can be controlled and if so how? I looked at the PDL API documentation but perhaps I am missing it ?
Thanks,
Wess
Show LessHello,
I read TRM to erase Flash Row but I can not find the address of IPC_STRUCT.DATA in Registers TRM.
It seems that API is prepared for assess the register but I can not find the API in any documentation.
Please let me know how to access the register.
Best regards,
Show LessHi,
I am trying to trigger an interrupt on MC4 using IPC notify on CM0+.
I am failing to verify that the interrupt is indeed triggered on CM4.
Here is what I am doing:
- I am using the Dual Core Shared Memory example code as my basic code.
- On MC0+ (main_cm4.c):
- Enabling interrupts: __enable_irq();
- Mask (enable) interrupts:
IPC_INTR_STRUCT_Type *myIpcHandleInt;
myIpcHandleInt = Cy_IPC_Drv_GetIntrBaseAddr(MY_IPC_CHANNEL);
Cy_IPC_Drv_SetInterruptMask (myIpcHandleInt, 0xFFFF, 0xFFFF);
- Sending 1 as the notification event interrupt to Cy_IPC_Drv_SendMsgPtr(): Cy_IPC_Drv_SendMsgPtr(myIpcHandle, 0x1ul, &sharedVar)
- On CM4 (main_cm4.c):
- Enabling interrupts: __enable_irq();
- Enabling IPC IRQ: NVIC_EnableIRQ(41); // 41 denotes CPUSS Inter Process Communication Interrupt #0
- Mask (enable) interrupts:
IPC_INTR_STRUCT_Type *myIpcHandleInt;
myIpcHandleInt = Cy_IPC_Drv_GetIntrBaseAddr(MY_IPC_CHANNEL);
Cy_IPC_Drv_SetInterruptMask (myIpcHandleInt, 0xFFFF, 0xFFFF);
I am trying to verify the interrupt indeed occurred by using the debugger on CM4, and placing a break-point at the Default_Handler (startup_psoc63_cm4.S).
What am I missing?
** The project is attached.
Use CE216795_DualCoreSharedMemory01.cyprj as the project file.
Thanks
Show LessHello
I am trying to create Eagle library for CY8C6247BZI-D44. For that I need package drawing as mentioned on page 56 of its datasheet.
I am unable to find this drawing "001-97718".
Looking forward ...
Thanks
Show LessHi,
I'm communicating with an SPI device (PSoC 63 is MASTER) which expects CPOL=0 CPHA=1, however when I try set it like that in ModusToolbox I noticed the SCLK line is idle high not low. Code generated has CY_SCB_SPI_CPHA1_CPOL0 set for sclkMode in the _config .
After tweaking with the settings I got it to work, but only when I use CPOL=1 CPHA=0 (CY_SCB_SPI_CPHA0_CPOL1 sclkMode). That way the clock line is idle low and active high as expected for CPOL=0 and the phase seems to actually match what I'd expect to be 1.
Am I just very confused about how this is supposed to work or is there a real problem here?
This is using ModusToolbox 1.1. Screenshot shows logic trace of the device working correctly on CY_SCB_SPI_CPHA0_CPOL1, but to me this isn't really CPOL1 at all.
Thanks
Show Less