PSoC™ 6 Forum Discussions
Hi everyone, I am trying to get started with the PSoC6 BLE examples and have encountered an error regarding the upgradable stack example:
Setup:
- PSoC Creator: 4.2
- PDL: 3.0.4 (also tested with 3.0.1, which is the library used in the example, same results)
- Compiler: GCC (standard GCC provided with PSoC Creator)
- Example code: CE220960 - PSoC 6 MCU BLE Upgradable Stack Bootloader (code unchanged, see any change to config below)
Problem:
- Launcher (app0): compilation with no error
- Bootloader (app1): does not compile unless the post scrip configuration of the CM0p core is changed from
"post_build_core1.bat creator ${OutputDir} ${ProjectShortName} GCC" to empty.
I think the main problem might be in this step. - Application (app2): does not compile and returns the following error:
"./bootload_cm4.ld:243: non constant or forward reference address expression for section .cy_boot_ble_bss"
I might be missing something very basic but since the code has not been modified in any way from the example I thought it might be worth sharing to understand if this is a an issue anyone else had encountered.
Thank you!
Show LessDear sir, good day
I'm just starting to learn PSoC. I want to understand the following: can I create, for example, a shift register for 24 outputs?
TIA
Sincerely
Vladimir Naumenkov
www.agat.by
Show LessGreetings All!
I'm using a PSOC6 BLE development kit, and I want to add several ADCchannels of sigma delta converters. The PSOC6 doesn't have enough space in its programmable logic to accommodate 4 sigma delta interface (each has a sinc3 filter, a decimator, and runs at a delta sigma sampling rate of 10 to 20MHz).
In order to account for this, I have the sigma delta converters on board a Lattice Machxo3 development board. What I want is to make the Machxo3 look like a memory interface to the PSOC, so that I can use the EMIF interface. In this way, the PSOC would read external memory addresses every so often, which are actually the conversion results of the 4 sigma delta converters. I'm hoping to get a sampling rate of ~100kHz.
I don't have much experience with memory types or EMIF - is it easier to make the FPGA look like an asynchronous memory, or a synchronous memory?
Show LessI am trying to debug the CM4 core. I select the CM4 as the debug target and click on Debug. The resume (F5) is grayed out. I can add breakpoints but I have no way to resume.
How do I get to my breakpoint?
Show LessThis thread is a year old but I am having the same problem... I have tried adding the library as 'm' and as 'libarm_cortexM4lf_math.a' but the PSOC creator keeps complaining. I have tried relative paths as well as absolute path.
Thanks
Trampas
Show LessRunning on a PSoC 6 from PSoC Creator 4.2. I don't seem to get much of a stack in the Call Stack pane after a failed assert, which makes debugging extremely difficult. While trying to find if others have run into this, I saw some examples where others had the full call stack available. Is there some setting I'm missing?
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With previous PSoC generations, routing DMA requests and interrupt requests to external pins was a good way to debug DMA configurations with a logic analyzer. When I try to do this on a PSoC 6, I get a placement error. Is there some workaround that would allow me to see an interrupt signal from a DMA component on a GPIO?
Show LessHello,
I am working on an application which uses bootloader and main application. I am using PSoC Creator 4.2 for development. In the main application I want to use the Emulated EEPROM component. I am creating the .cyacd2 file with the tool cymcyelftool.exe from PDL, and updating the firmware with this created file. The issue I face is that every time I update the firmware, my EEPROM is erased. I see that in .cyacd2 file there are memory addressees which are from Emulated EEPROM area and this is what cause the issue, because bootloader will write to these locations. Is there a way to exclude this EEPROM area from the .cyacd2 file?
Thanks,
Stefan.
Show LessHi sir,
I'm using psoc creator 4.2 run demo: CE218136_EINK_CapSense_RTOS ,everything is ok if uart component is disable.
When i enable uart component and #define UART_DEBUG_ENABLE (true),code will loop in vTaskStartScheduler() ,
how can i makesure this issue,please help to check,thanks.
Best Regards,
Leo
Show Less