I'm using CYC8KIT-062S4, FWIW.

When I create the Dual-CPU Empty PSoC6 App, I see a file called system_psoc6.h located under bsps\TARGET_APP_CYC8KIT-062S4.  The instructions in linker.ld advise changing the CY_CORTEX_M4_APPL_ADDR value in this file to reflect the length of the CM0P application.  This worked in MTB 2.4, however it no longer has any effect in MTB 3.0.  The reason appears to be that CY_CORTEX_M4_APPL_ADDR is already defined when this header is included--but where?

I changed my CM0P application to have a length of 0x8000.  I then changed the definition in system_psoc6.h to look like this:

#if !defined (CY_CORTEX_M4_APPL_ADDR)
	#define CY_CORTEX_M4_APPL_ADDR          (CY_FLASH_BASE + 0x8000U)
#endif /* (CY_CORTEX_M4_APPL_ADDR) */

Upon running the application, I see a crash when the M4 is enabled.

If I comment out the 'if !defined' like so...

//#if !defined (CY_CORTEX_M4_APPL_ADDR)
	#define CY_CORTEX_M4_APPL_ADDR          (CY_FLASH_BASE + 0x8000U)
//#endif /* (CY_CORTEX_M4_APPL_ADDR) */

...and rebuild, I get a ton of 'redefined' warnings, however the application then runs correctly.

Seems like the instructions in linker.ld could use an updating?

I am using CE219431 which demonstrates using a PDM mic. The example sets a threshold at 128 samples in the fifo before the interrupt is supposed to be triggered, but it seems the interrupt is being triggered immediately after clearing a couple times. I am using PDM_PCM_GetNumInFifo() to get and then print out how many are in the fifo every time the mic flag is set, and the pattern is 129 samples, 1 sample, 1 sample, 129 samples, 1 sample, 1 sample, etc. So basically the interrupt is tripped 2X more often than it should be which is annoying for my application. I have tried messing around with the order of clearing the interrupt and reenabling and resetting the flag, but I can't figure out what the problem is. I also thought it could be that the fifo count needs more time to be updated before interrupts are enabled, or it will trip it, but I added a 5ms delay after reading the fifo, and that didn't have an effect on the extra interrupt triggers. 

Anybody else figure this one out?

Thanks for reading my post!

Josh

HI ,

for a new project I have to implement the reading of a rotary encoder on CY8CPROTO-63-BLE PSOC6.. I don't understand if this functionality with the PDL QUADDEC feature is present in the CYBLE-416045-02 chip and what are the dedicated PhiA, PhiB pad pins and if there is a configuration example project in the designer Psoc creator 4.3

Thanks in advance

Robert 

Hi,

I need to get 24 channels of ADC into the PSoC 63 (124 BGA).
max read-frequency is say 1kHz, x 24ch, I'd be ok with slightly less too.

I've built a project using AMux, it allows me to configure 24 connections while 8 of course will be placed on port10 which is directly tied to the ADC. The remaining pins will be routed in fabric. 

Questions:

1. How do I best find out / calculate the limits of the MUX vs the SARADC speed?
   
   
2. Please see attached screenshot which says "SARADC is reachable through analog routing fabric but my lead to congestion or failure"... 
   Is there a way in psoc creator (or modus) to get more info on what the actual limitations might be?

Hello, 

 

 

 

Hi all,

Using New Application: if I select empty  project (or is it empty BSP?) on the first screen where I can choose the kit, then I can choose empty project but there is no dual core ... if I select a kit on the first screen then I see a dual core empty app but I don't want to select a kit. It seems to add more stuff I don't care for because I have my own board.

What am I missing? 

BTW nice improvements with Modustoolbox 3. BSP Assistant is great! Nice job guys/gals.

Thanks