PSoC™ 6 Forum Discussions
The model I'm using now is Cy8ckit-062-wifi-BT. When I run the sample project for this model, I can find the GUI.h header file, but when I create my own project, I get an error because I can't find the GUI.h header file. Why is this happening, and is there any solution? If it's because the header file is missing, can I just copy the GUI.h in the sample project to the folder of the project I created? But I don't really know the exact location of the folder, can you help me point it out?
Also, I quit the software after running the project, and I can't modify the code when I open the project again. What is the reason for this? What should I do to revise and modify the code?
Hello Team Cypress, I am using Psoc 6 series microntroller CY8CKIT-062-WIFI-BT and currently i am trying to debug example memory code SERIAL FLASH READ WRITE . I want to know the address where the memory is stored and how can i view that location.
Show LessI'm wanting to add a DFU bootloader for the PSOC61 (I'm using the CY8C6148AZI-S2F44 MCU) using the USB peripheral.
I was hoping to use the mtb-example-psoc6-dfu-basic example but this is for the PSOC62 dual core devices. Just wondering if anyone has implemented this for the Single core PSOC61 device? Or if there is any advice on how to modify the example code for a single CM4 core?
Regards
Dave
Show LessDears,
The Basic_Device_Firmware_Upgrade example for CY8CKIT-062-WIFI-BT was created with DFU V4.2.
The latest DFU version is 5.0. When will the example using this be released?
Thanks and Regards,
YS
Hi,
I'm taking my first steps with the CY8CPROTO-063-BLE platform and wanted to create my own boot code outside the ModusToolbox ecosystem. After programming the board, I try to debug this small boot code. However, the CM0+ core seems to be stuck on what I believe is the secure bootloader/ROM boot. I am running from FLASH. I have a couple of questions:
-
Is there any possibility to disable the ROM boot on this platform?
-
If disabling the ROM boot is not an option, what factors should I consider while developing my application outside the ModusToolbox environment?
Thanks
Show Less请问有 关于PSOC 6 上的 CRC和ECC 硬件校验算法的例程 程序吗 ?
Psoc是支持 硬件ECC加密吧? 请问有例程吗我有几个问题请教一下:
1 单核的程序,一个Bootloader和一个APP。
1)关于APP的linker文件配置,我不清楚CM0应该配置跟boot一样还是不一样。
boot程序的CM0:0x10000000~ 0x10002000, CM4:0x10002000~0x10010000.
我预想的 boot程序在CM4完成,flash范围 0x10002000~0x10010000,APP 也是CM4完成,调试阶段暂定0x10010000~最后
我的疑问是APP的CM0应该怎么设计呢?我上面的预想有没有问题?
实际运行的跳转过程是这样吗 boot cm0-->boot cm4--->appcm4?
2)实际升级时app里面的hex是CM0和cm4一起生成的hex吧,所以我上面的跳转过程是不是不对?需要改为boot cm0-->boot cm4--->appcm0->appcm4?并按这个过程重新定义flash的地址分配?
3)跳转函数:
之前帖子有回复我跳转函数:
2 其实搞这个方案还是因为我的双核方案里cm0里面操作flash死掉了,我没有sleepcm0,也没有启动cm4,不知道问题在哪。
Hi, all,
This question is somewhat "return of the previous question".
In the previous quesiton, the solution was to use ellisys sniffer.
But as the customer does not have such tool(s) to measure the RF wave,
they want to output the timing of BLE wave generation via UART.
IMO, as only _write() function calls 10ms delay, UART signal can not be a good method to measure the communication interval timing.
So my quetion in this question is,
Can we output BLE wave generation timing via GPIO?
Or is/are there method to let the customer measure communication interval timing only using oscilloscope?
moto
Show Less
Hi all,
I have a very interesting problem that I havent been able to solve for days. I have two different computers and they are setup to be the same.
On one computer, the RX FIFO buffer (RX_FIFO_RD) can be corrected referenced to /mtb_shared/mtb-pdl-cat1/release-v3.7.0//devices/COMPONENT_CAT1A/include/ip/cyip_scb.h. It builds compiles and runs.
On the second computer, the same RX_FIFO_RD cannot be resolved, and asks me to select which header to use cyip_ble.h, cyip_i2c.h and cy_scb.h from COMPONENT_CAT1A, COMPONENT_CAT1B or COMPONENT_CAT1C. It seems that it just cant make the link to the correct header after using 'Device Configurator'.
I cannot for the life of me find out why this isn't working properly on the second computer. Thanks for your help
Code snippet is below:
void configure_rx_dma(uint32_t* buffer_a, uint32_t* buffer_b, cy_stc_sysint_t* int_config)
{
cy_en_dma_status_t dma_init_status;
const cy_stc_sysint_t intRxDma_cfg =
{
.intrsrc=sRx0_IRQ,
.intrPriority = 7u
};
// -------------------------------------------------------------------------------------------------
// SCB0 Slave 0
// -------------------------------------------------------------------------------------------------
/* Initialize SCB0 descriptor 1 */
dma_init_status = Cy_DMA_Descriptor_Init(&sRx0_Descriptor_0, &sRx0_Descriptor_0_config);
if (dma_init_status!=CY_DMA_SUCCESS)
{
handle_error();
}
/* Initialize SCB0 descriptor 2 */
dma_init_status = Cy_DMA_Descriptor_Init(&sRx0_Descriptor_1, &sRx0_Descriptor_1_config);
if (dma_init_status!=CY_DMA_SUCCESS)
{
handle_error();
}
// Initialise DMA channel 20 (corresponds to SCB2 rx)
dma_init_status = Cy_DMA_Channel_Init(sRx0_HW, sRx0_CHANNEL, &sRx0_channelConfig);
if (dma_init_status!=CY_DMA_SUCCESS)
{
handle_error();
}
/* Set for (SCB0) source and destination address for descriptor 1 */
Cy_DMA_Descriptor_SetSrcAddress(&sRx0_Descriptor_0, (uint32_t *) &sSPI0_HW->RX_FIFO_RD);
Cy_DMA_Descriptor_SetDstAddress(&sRx0_Descriptor_0, (uint32_t *) buffer_a);
/* Set for (SCB0) source and destination address for descriptor 2 */
Cy_DMA_Descriptor_SetSrcAddress(&sRx0_Descriptor_1, (uint32_t *) &sSPI0_HW->RX_FIFO_RD);
Cy_DMA_Descriptor_SetDstAddress(&sRx0_Descriptor_1, (uint32_t *) buffer_b);
// All the lines above sets stuff for the descriptor structure
// The follow line sets the current(starting) DMA descriptor state, so will start with descriptor 0
Cy_DMA_Channel_SetDescriptor(sRx0_HW, sRx0_CHANNEL, &sRx0_Descriptor_0);
/* Initialize and enable interrupt from RxDma */
Cy_SysInt_Init(int_config, &rx_dma_complete); // system interrupt for CPU
NVIC_EnableIRQ(int_config->intrSrc);
/* Enable DMA interrupt source. */
Cy_DMA_Channel_SetInterruptMask(sRx0_HW, sRx0_CHANNEL, CY_DMA_INTR_MASK);
/* Enable channel and DMA block to start descriptor execution process */
Cy_DMA_Channel_Enable(sRx0_HW, sRx0_CHANNEL);
Cy_DMA_Enable(sRx0_HW);
}