PSoC™ 6 Forum Discussions

Is it possible to debug both cores simultaneously in uVision 5.28a?  This KBA (PSoC 6 MCU Multi-Core Debugging with Third-Party IDEs – KBA222959 ) notes that Eclipse is able to do it.  Can uVision?  And what debugger tools work for this task?

*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'

Build Project 'M4' - Target 'Target 1'

linking...

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(126): warning: L6314W: No section matches pattern *(.cy_app_signature).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(136): warning: L6314W: No section matches pattern *(.cy_em_eeprom).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(145): warning: L6314W: No section matches pattern *(.cy_sflash_user_data).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(154): warning: L6314W: No section matches pattern *(.cy_sflash_nar).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(163): warning: L6314W: No section matches pattern *(.cy_sflash_public_key).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(172): warning: L6314W: No section matches pattern *(.cy_toc_part2).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(181): warning: L6314W: No section matches pattern *(.cy_rtoc_part2).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(191): warning: L6314W: No section matches pattern *(.cy_xip).

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\cy8c6xx7_cm4_dual.scat(201): warning: L6314W: No section matches pattern *(.cy_efuse).

Program Size: Code=13182 RO-data=2174 RW-data=692 ZI-data=109224 

Finished: 0 information, 9 warning and 0 error messages.

FromELF: creating hex file...

After Build - User command #1: C:\Keil_v5\ARM\PACK\Cypress\Pack\2.0.0\Device\CY8C6347BZI-BLD53_Pack\Other\postbuildCortexM4.bat "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\M4.axf" "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\" "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\" "cmsis" "C:\Keil_v5\ARM\PACK\Cypress\Pack\2.0.0\Device\CY8C6347BZI-BLD53_Pack\Other\win\elf"

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild>IF /I "cmsis" NEQ "cmsis" GOTO not_cmsis

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild>copy /Y "C:\Keil_v5\ARM\PACK\Cypress\Pack\2.0.0\Device\CY8C6347BZI-BLD53_Pack\Other\win\elf\cymcuelftool.exe" "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\\cymcuelftool.exe"

已复制         1 个文件。

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild>move /Y "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\M4.axf" "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\\M4_link.axf"

移动了         1 个文件。

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild>for %i in ("E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\\Objects\*_link.axf") do @(IF "%i" NEQ "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\\M4_link.axf" set MergeFiles=!MergeFiles! "%i" )

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild>set MergeFiles="E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\\M4_signed.axf"

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild>"E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\\cymcuelftool.exe" --sign "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\\M4_link.axf" --output "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\\M4_signed.axf"

No ELF section .cychecksum found, creating one

Application checksum calculated and stored in ELF section .cychecksum

Checksum calculated and stored in ELF section .cymeta

E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild>"E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\\cymcuelftool.exe" --merge "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\\M4_signed.axf" --output "E:\Work\18.reflex-PPG\Software\Cypress-Prj\Cy-V0.001\VitaBle.cydsn\uVisionBuild\ObjectsM4\M4.axf"

Expected at least 2 elf file arguments for -M/--merge

Usage:

Display help:

   cymcuelftool -h/--help

Display version information:

   cymcuelftool -v/--version

Display memory allocation by type:

   cymcuelftool -A/--allocation file.elf

Merge ELF files:

   cymcuelftool -M/--merge complete_app1.elf complete_app2.elf ... [--output merged.elf] [--hex merged.hex]

Sign ELF file, with option for secure (encrypted) signature:

   cymcuelftool -S/--sign unsigned.elf [<SignScheme>] [--output signed.elf] [--hex signed.hex]

Generate Patch file:

   cymcuelftool -P/--patch file.elf [--encrypt <Cipher*> --key key.txt [--iv iv.txt]] [--output patch.cyacd2]

   *NOTE: RSAES-PKCS and RSASSA-PKCS not allowed for this command

Create Code sharing file:

   cymcuelftool -R/--codeshare file.elf symbols.txt <GCC/ARMCC/IAR> [--output shared.s]

<SignScheme> is only used for signing the user application. It must be ONE of:

   1) HMAC <Hash*>  --key key.txt              (*CRC not supported)

   2) CMAC-AES-XXX* --key key.txt              (*XXX can be 128, 192, or 256)

   3) <Hash> [--encrypt <Cipher> --key key.txt [--iv iv.txt]]

<Hash>: CRC, SHA1, SHA224, SHA256, SHA384, SHA512

<Cipher> (requires key):

   Public-key: RSAES-PKCS, RSASSA-PKCS

   Symmetric:  DES-ECB, TDES-ECB, AES-{128|192|256}-{ECB|CBC|CFB}

key.txt: ASCII text file containing key appropriate for chosen Cipher. May be symmetric hex key or PEM format for RSA cipher variants

iv.txt:  ASCII text file containing initialization vector for certain encryption algorithms

".\ObjectsM4\M4.axf" - 0 Error(s), 9 Warning(s).

Build Time Elapsed:  00:00:02

Hi.  So, coming from a good understanding of the PSOC5LE and PSocCreator, I'm trying to come to understand the PSOC6.  I have 3 tools available, the Modulus Toolbox, WICED Studio and PSOC Creator, each capable of running my kit (CYKIT_062 BT-WIFI).

PSOC Creator creates an LCD component in the fabric which handles the TFT display, WICED Studio has some hidden UDB for some of the pins (8 parallel pins tied to a UDB register) and bit-bangs the rest, Modulus Toolbox does totally bit-banging.  Three distinct different ways across three different tools.

I want to use the PSOC Creator method against the Modulus Toolbox environment.   But, where is the fabric programmed?  Is it some hidden .elf file that needs to be linked in?   Where can I get the output from PSOC Creator and use it for something else?   Where does the hidden UDB come from in WICED studio?

Could someone help me understand how the digital fabric is programmed with this tools?

hi  Cypress:

    when i use Psoc6 to printf  float , it shows noting  the code is below: it can output float date?

void My_Uart_Init(void)

{

    cy_en_scb_uart_status_t uart_status ;

    uart_status  = Cy_SCB_UART_Init(Uart_Printf_HW, &Uart_Printf_config, &Uart_Printf_context);

    if(uart_status != CY_SCB_UART_SUCCESS)

    {

        HandleError();

    }

    Cy_SCB_UART_Enable(Uart_Printf_HW);

}

int _write(int file, char *ptr, int len)

    {

        int nChars = 0;

        /* Suppress the compiler warning about an unused variable. */

        if (0 != file)

        {

        }

        nChars = Cy_SCB_UART_PutArray(Uart_Printf_HW, ptr, len);

        return (nChars);

    }

static void HandleError(void)

{

     /* Disable all interrupts */

    __disable_irq();

    while(1u)

    {

    }

}

Test Code:

float a = 1.234;

int main(void)

{

    __enable_irq();

    My_Uart_Init();

    for(;;)

    {

         printf("a = %f\r\n", a);

         CyDelay(500);

    }

}

输出解决:

Dear  Cypress:

   when i test psoc6 ipc demo code  of  CE223820, it can't pass the build, it show :

main_cm0p.c:56:17: error: 'CY_SYS_CYPIPE_INTR_MASK' undeclared here (not in a function)

so  what 'CY_SYS_CYPIPE_INTR_MASK' should be define??  TKS;

Hello guys,

I am working on my graduation project, which uses cy8ckit-062-ble to receive the temperature change and display it on the app of the mobile phone via Bluetooth. But now I want to connect it to the cloud (such as AWS) to monitor the change of temperature. Can this be realized?

Regards,

Yang

We're using the CYM943012P6EVB-01 Rev2.2 kit. We have successfully built and run mbed-os-example-blinky and mbed-os-example-capsense with mbed cli as well as several projects using WICED. Using a second CYM kit board that we modified (see below for a short discussion of our CYM board modifications) to disconnect J-LINK from the on-board PSoC62 so we could connect it to our own board without contention. Just like the CYM board, our board also has the PSoC62 and a Murata BLE/WiFi chip (may not be exactly the same as the kit Murata part as the designations on the chip differ).

At one point, we were able to program this just fine but now whenever we program using DAPLink mode (either direct copy of a .hex file to the DAPLink volume or using the mbed command), the chip resets, DAPLink comes back online, and we have a FAIL.TXT file.

What is the board trying to tell me? What am I doing wrong? Again, please note that I have no trouble doing the below with an unmodified kit board; the issues arise when working with a modified kit board with our board connected to the JLink ports.

The rest of this post provides version information, commands run, terminal output from those commands, and finally the contents of FAIL.TXT.

For reference, we're using

- mbed 1.10.1

- ARM GCC version 6.5.0

$ mbed detect

[mbed] Working path "~/work/matrix-reloaded/cypress/mbed-os-example-blinky" (program)

[mbed] Detected CYW943012P6EVB_01, port /dev/ttyACM0, mounted /media/.../DAPLINK, interface version 0254:

[mbed] Supported toolchains for CYW943012P6EVB_01

| Target            | mbed OS 2 | mbed OS 5 | uARM |    IAR    |    ARM    |  GCC_ARM  |

|-------------------|-----------|-----------|------|-----------|-----------|-----------|

| CYW943012P6EVB_01 |     -     | Supported |  -   | Supported | Supported | Supported |

Supported targets: 1

Supported toolchains: 3

$ fw-loader/bin/fw-loader --device-list

Cypress Firmware Updater, Version: 2.2.10.261

(C) Copyright 2018-2019 by Cypress Semiconductor

All Rights Reserved

Info: Start API initialization

Info: Connected - DAPLink CMSIS-DAP-19001301c8121a0b00c8121a00000000000000002e127069

Info: Hardware initialization complete (263 ms)

Connected supported devices:

    1: DAPLink CMSIS-DAP-19001301c8121a0b00c8121a00000000000000002e127069

$ fw-loader/bin/fw-loader --update-kp3

Cypress Firmware Updater, Version: 2.2.10.261

(C) Copyright 2018-2019 by Cypress Semiconductor

All Rights Reserved

Info: Start API initialization

Info: Connected - DAPLink CMSIS-DAP-19001301c8121a0b00c8121a00000000000000002e127069

Info: Hardware initialization complete (260 ms)

Device 'DAPLink CMSIS-DAP-19001301c8121a0b00c8121a00000000000000002e127069' opened successfully

Info: Kit FW is in 'DAPLink' mode.  Upgrade file is 'KitProg3' ver. 1.13 b322.

Info: Connected - KitProg Bootloader-0B1A12C800287400

Info: Bootloader Version: Major 1, Minor 1, Build 40

Info: FW Upgrade to version: 1.13 b322

Info: Bootloading of KitProg FW...

Info: Disconnected - DAPLink CMSIS-DAP-19001301c8121a0b00c8121a00000000000000002e127069

Info: Verifying of KitProg FW...

Info: Bootloading of DAPLink...

Info: Verifying of DAPLink...

Info: Upgrade completed

Info: Disconnected - KitProg Bootloader-0B1A12C800287400

Info: Connected - KitProg3 CMSIS-DAP BULK-0B1A12C800287400

Warning: Wait for upgraded device is timed out

FW update completed successfully

Then I power on the kit but leave our board in reset. The kit comes up with LED1 and LED3 solid amber. I press SW3, LED3 switches to 1Hz pulsing amber. After pressing it again, LED3 switches to 2 Hz pulsing amber, indicating the board is in DAPLink mode (as described in KitProg3 User Guide). Then I release our board from reset. I see activity in LED2 (rapid blinking red) and LED4 (rapid blinking green). Once the blinking stops, I try to flash the board (note that in the below, the compilation was done previously, so it jumps right to flashing the board).

$ mbed compile --target CYW943012P6EVB_01 --toolchain GCC_ARM --flash

[mbed] Working path "~/work/matrix-reloaded/cypress/mbed-os-example-blinky" (program)

Building project mbed-os-example-blinky (CYW943012P6EVB_01, GCC_ARM)

Scan: mbed-os-example-blinky

Link: mbed-os-example-blinky

Elf2Bin: mbed-os-example-blinky

| Module                |     .text |    .data |     .bss |

|-----------------------|-----------|----------|----------|

| [fill]                |   130(+0) |    3(+0) |   43(+0) |

| [lib]/c.a             | 27253(+0) | 2472(+0) |   89(+0) |

| [lib]/gcc.a           |  3168(+0) |    0(+0) |    0(+0) |

| [lib]/misc            |   252(+0) |   16(+0) |   28(+0) |

| [lib]/wiced_drivers.a |  1677(+0) |    0(+0) | 1728(+0) |

| [misc]                |     8(+0) |   88(+0) |    0(+0) |

| main.o                |  1169(+0) |    4(+0) |   16(+0) |

| mbed-os/cmsis         |  1033(+0) |    0(+0) |   84(+0) |

| mbed-os/components    |   120(+0) |    0(+0) |    0(+0) |

| mbed-os/drivers       |  1738(+0) |    0(+0) |    0(+0) |

| mbed-os/features      |   376(+0) |   16(+0) |  240(+0) |

| mbed-os/hal           |  2337(+0) |    8(+0) |  152(+0) |

| mbed-os/platform      |  5951(+0) |  260(+0) |  318(+0) |

| mbed-os/rtos          |  8666(+0) |  168(+0) | 5973(+0) |

| mbed-os/targets       | 20634(+0) | 1337(+0) | 1041(+0) |

| Subtotals             | 74512(+0) | 4372(+0) | 9712(+0) |

Total Static RAM memory (data + bss): 14084(+0) bytes

Total Flash memory (text + data): 78884(+0) bytes

Image: ./BUILD/CYW943012P6EVB_01/GCC_ARM/mbed-os-example-blinky.hex

[1570808185.90][mbedls.platform_database]Duplicate platform ids found: daplink.1900, ignoring the definitions from ~/.local/share/mbedls/platforms.json

$ cat FAIL.TXT

error: Flash algorithm erase sector command FAILURE

type: target

CYM Board Modifications

We ​removed resistors R24, R25, R130, R131, and R26 and then connectrf over JLink we only run TMS_SWDIO and TCLK_SWCLK plus VCC and GND over JLink. Since we're handling reset ourselves, this should work fine (see https://www.segger.com/products/debug-probes/j-link/technology/interface-description/)

I want to change the lifecycle stage with Cypress Programmer CLI the same way I can do it with the PSoC Programmer COM API PSoC6_WriteProtection().  I just want to change lifecycle to secure and modify nothing else related to protection.  I think one way to do it is with psoc6 allow_efuse_program <on> and then program a hex file with the efuse bit for secure set to 1.  I don't want to destroy any boards testing this.  Can someone give me a tested solution for CY8C6247FTI-D52?  Thanks.

I'm using psoc63 on my custom design board.I have configured ble as GAP peripheral and GATT server role and selected only cm0  core for ble operation. But after generating all the ble files, when using some api function like Cy_BLE_GAPP_StartAdvertisement it shows error stating "implecit declaration of function".