PSoC™ 6 Forum Discussions

Hi ,

    In the PSoC6 design, uart component is different  from PSoC4, there is no "wake up from deep sleep" option. So we don't know how to use the uart to wake up from deep sleep. From the spec of PSoC6 low-power mode, there is only retention the I2C/SPI wake up available. It means that uart can not use for wake up ?  Or is there any other solution for wake up form the uart rx pin?  Thanks!

Hi all,

when are SMPU master/slave protection structures reset or cleared?

My goal is to try to mimic Secure state and keep a chip in Normal state. I was thinking to setup SMPU to totally disable DAP master (It will not have any read/write/execute permission) and ensure that only PC 0 can enable DAP again. Is such thing possible?

It looks that SMPU setting survives power cycle and only device reset from the PSoC Programmer software clears it.

Regards

Ondrej

I am using CY8CKIT-002 PSoC MiniProg3 program and debug kit to debug some custom build PSoC 5lp boards. I am facing some issue while connecting to the debugger, I had an issue with the driver, I installed the latest  MiniProg3 (3.4.1.20), driver. I am able to see the device in the Device Manager properly.

The problem I am facing right now is while using the PsoC Programmer, The Programmer is able to connect to the MiniProg3, when it tries to open the Port after waiting for a few seconds it displays "Failed Connect to  at 12:06:42 AM | Firmware is not fully loaded and device cannot be detected. Please reconnect - "MiniProg3/1803CA0008D3". as shown in below image.

Is there any way to resolve this issue,  Any help will be appreciated.

Could BLE sub system get into deep sleep while using ILO. I have tried to change CLK_LF source from WCO to ILO but it didn't work, could anyone help how can I do this ?

We are trying to use hard FPU in PSoC 6, but in core_cm4.h FPU requires setting __SOFTFP__ into 0u:

however, it seems PSoC creator is using soft FPU by default:

In this thread, GeonaM_26​ has explained how to make new Makefile to change softfp into hardfp:https://community.cypress.com/thread/32197?q=Using%20hard%20FPU

but, this requires compiling the whole project outside of PSoC creator. Is there any way to change this parameter without manipulating a Makefile?

I have a project to use SPI communication.I need to change the register values of the module I will communicate with.

adress==>6F    (function ==>TX Data Rate 0)      (txdr[7])     (txdr[6])     (txdr[5])     (txdr[4])     (txdr[3])     (txdr[2])     (txdr[1])     (txdr[0])       ======>3Dh

                                                                                  0                   0             1                1              1                 1                 0                1

I want to upload 3dH to 6F adress.

PSOC3==> 8051

PSOC35  and PSoC6 ==> ARM cortex

Since PSOC3 is 8051, I should prefer my PSOC3.

Hello,

I have a bootloadable project set up as BLE a peripheral with LE secure and bonding data stored to emEEPROM. I'm experiencing a hard fault when connecting to a BLE central. I've tracked the hard fault to inside the llh_isr_handler within the cy_ble_stack_mdk_soc_cm0p.a library, so I'm hoping someone here can provide some insight.

The BLE component is set up to run on a single core on the CM0+ and everything works ok (can connect to BLE central, bond, save bonding information to emEEPROM) if I disable the CM4 by calling Cy_SysDisableCM4() in the CM0+ main function. However, if I enable the CM4 (after BLE stack is up, to avoid any flash contention with EEPROM), when I try to connect a BLE central, the hard fault appears. All of this happens when I am using the linker scripts that put this bootloadable application in the appropriate location to support DFU. However, if I compile the image as a standalone program (linker script changes so flash start for m0 = 0x10000000), I no longer get the hard fault and I can connect+bond without issue.

So, I'm having trouble explaining these things. If there was some contention between the M4 and M0, I don't understand why moving the image around would fix the issue. If the location in flash makes a difference, what setting to I need to change to make things work in the bootloadable application? Does anyone have insight into what could cause this issue?

Thanks,
Theo

I have a project with an ADC wired as follows:

and configured as follows:

VDDA is 3.3V.  When I feed a voltage of 2.00V into VBatIn, I get a result of approximately 430 counts, which comes out to approximately 1.4V.  The behaviour is the same if I buffer the signal internally with an Opamp component.

Is something misconfigured here?  What do I need to do to get the right values coming out of the ADC?

I am trying to use LIN module with CY8CKIT-062-WIFI-BT using PSOC Creator 4.2. I am having difficulty finding instruction on how to enable LIN module  on POSC 62.

After going through couple of online blog I found that current POSC 6 chip is not automotive qualify and not supporting LIN at this moment.

I like to know Cypress Plan to release LIN Plug in for PSOC 61 and will it be available for Psoc Creator or Modus Tool box or both.

Hello.

I am making the bootloader of PSoC 6 based the CE22096001.

The bootloader work well on the CY8C6347BZI-BLD53.

My customer changed the device to the CY8C6337BZI-BLF13.

The device is one core(cortex-M4).

After changing to the device, the CE22096001 was compiled normally.

But, I don't test the firmware yet because I don't have the CY8C6337BZI-BLF13.

Does the CE22096001 work on the CY8C6337BZI-BLF13?

The cortex-M4 start addresses of the CE22096001 are 0x10003000(app0), 0x10008000(app1), 0x10043000(app2).

How does the cortex-M4 boot without the cortex-M0?

If the cortex-M0 works at behind, Where is the cortex-M4 start address saved?

Thanks and best regards.

Glenn.