PSoC™ 6 Forum Discussions
We are looking to interface a PSOC 6 to an LTC2324-16 ADC (16 bit conversions) with a PSOC6. The LTC2324 is a 4 channel, simultaneously sampled ADC, with an SPI interface (each ADC conversion is a 64-bit transaction). However, to increase throughput, there are 4 simultaneous MISO outputs (slave to master data). In this way, the ADC can send out data 4 times as fast (I.E. it has 4 "MISO lanes" to get the data out faster [4 outputs, each stream is 16 bits], as opposed to a conventional single MISO that 4 ADC results are daisy-chained to [1 output stream at 64 bits]).
Normally, stock PSOC components do not support this 4-lane MISO interface. In order to interface this custom ADC to a PSOC6, I was going to use a regular SPI master interface with no MISO pin, and then I will make 4 digital input pins with a shift register behind each pin:
(15 D-type flip-flops per input stream) X (4 inputs) = 60 flip-flops
All flip-flops would share the common clock generated from the LTC2324. I would then use Status registers (8 bits per status register --> 8 of them needed to read all 64 ADC bits) to get all 4 ADC results into the firmware.
--> Before I get too deep in the weeds, would this approach work? Am I missing something?
Show LessHello,
we are currently trying to port an audio WICED application running on 43907 to the CY8CPROTO-062-4343W board and Modustoolbox 2.0.
While the Wi-Fi part could be easily adapted, the audio part is more tricky.
The application handles full duplex audio streams through an I2S port, and unfortunately PSOC 6 SDK has no high level audio driver managing the transfer of audio periods, unlike WICED.
I just looked to port the PSOC 6 audio driver from WICED (WICED\platform\MCU\PSoC6\peripherals\platform_i2s.c, for PSOC 6 1M) but I found two annoying things:
A)
/*
* The I2S block consists of two sub-blocks:
* I2S Transmit (Tx) block: word select (tx_ws), clock (tx_sck) and data (tx_sdo) output signals.
* I2S Receive (Rx) block: word select (rx_ws), clock (rx_sck) and data (rx_sdi) input signals.
* When PSoC6 is driving both TX and RX as I2S Master, the TX and RX clock lines can be out of sync.
* If the TX/RX clock lines are connected together to an audio codec, it may not be able to output audio.
* In such settings, simultaneous RX and TX (full duplex I2S) audio can be achieved as follows:
* I2S transmitter is in slave mode.
* I2S receiver is in master mode.
* (Also note that AC spec. should be satisfied at the PSoC6 pin in order to function correctly)
*/
B) The copy of the audio data seems to not be performed with DMA at all, the CPU inserts each sample one at a time in the I2S FIFO:
static void service_transfer_complete( platform_i2s_direction_t dir )
{
...
if ( num_samples > 0 )
{
samples = (uint16_t*)(&(stream->audio_buffer_ptr[stream->position + stream->data_index]));
if ( dir == PLATFORM_I2S_WRITE )
{
length = (num_samples < (I2S_TX_FIFO_SIZE - I2S_TX_FIFO_TRG_LVL)) ? num_samples : (I2S_TX_FIFO_SIZE - I2S_TX_FIFO_TRG_LVL);
while ( length > 0 )
{
Cy_I2S_WriteTxData( i2s_base, (uint32_t)(*samples) );
samples++;
num_samples--;
length--;
stream->data_index += 2;
}
}
Does these limitations still apply to the PSOC 6 2M (found on the CY8CPROTO-062-4343W board) ?
If not, could you provide a code example to manage full duplex I2S with DMA transfers, and a higher level API than I2S PDL for PSOC 6 2M ?
Thank you.
Show LessI am migrating from the CY8KIT-062-BLE system that I used for prototyping, to making my own PCB with a PSoC6 6347BZI. I am wanting to utilize the FSUSB component, and despite following some of the available documentation, when I check for new components I cannot see the FSUSB. It appears in the PDL reference document (file:/C:/Program%20Files%20(x86)/Cypress/PDL/3.1.0/doc/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html ) but does not show up when I search for new components. Is there something I am not doing? I restarted the system after doing all the updates and configures.
Show LessHi Community,
After fiddling with shared memory I found my solution using pipes.
It's an easy way to communicate between cores on the PSoC6.
Problem:
I can't find any documentation or AN Aside from the CE223820 example.
I want to learn more about the usage of these pipes.
Show LessHello,
We can find the 128 LQFP package for PSoC62 and PSoC61 in CYPRESS web.
Are these already released?
If it is not yet, when do you prepare the samples and production?
Best regards,
Yocchi
Show LessGreetings!
Using the PSOC 6 Pioneer kit (PSOC 62 processor).
I have two PWM blocks that share the same clock source. Is there a way to create a phase shift, so that the two PWM outputs are synchronized, with a constant phase shift between them?
In other words, they are the exact same frequency and duty cycle, but one would be a delayed output of the other?
Show LessTo all,
I'm blogging this discussion and would appreciate any feedback and potential solutions.
I'm referring to the discussion started by Konrad in the link below:
PSoC 6 Pioneering Kit doesn't work after programming
In summary, Konrad had a CY8CKIT-062-BLE that appeared to no longer work. The answer turned out to be that he had updated the PDL library to 3.10 on his PDL components used. This made his project no longer operational. To be clear, the project programmed successfully into the kit but the project no longer performed the required function. To get his kit to work, he needed to revert the PDL library version to be used to an earlier version. Trust me, that is not as easy as it sounds. Hopefully someone (poke at Cypress tech support) can reveal a simpler method. I will elaborate my method below.
I had an identical CY8CKIT-062-BLE and had multiple example projects for that kit built and successfully running.
At one point later, I downloaded and installed the PDL library 3.10. The install defines this library version as the latest 'default' library for PDL. Here is a pic of "Tools\Options..." menu.
Additionally updating the PDL components to the later (3.10) versions forces the PDL library to load this new code during the "Generate Application" phase of the build.
Note: Reverting to an early version is not easy or obvious. Note to Cypress: It would be nice if I can first invoke the "Component Update Tool" at will. Then select a earlier version in the "New Version" field. This might be a simpler means of reverting the component version. Right now, it appears you can only invoke the "Component Update Tool" when there are updated versions of at least one component available.
CAUTION!!!
There appears to be some updated PDL components that make the project non-operational.
I learned that the hard way. I automatically updated my PDL library and components to the latest (3.10) then all of a sudden my projects became nonfunctional whereas before I was operational. I thought my CY8CKIT-062-BLE was toast.
The "Fix"
To fix my issue, I had to take two steps:
- Load the original example project with the earlier version of the PDL component called out in the TopDesign. The downside of this method is any changes to the TopDesign or SW could be potentially lost. [Can Cypress suggest a better way to revert the component to an earlier version?)
- Go to menu "Tools\Options..." and selected an earlier version of the PDL library as shown in this pic.
Rebuild the project. This fixed my non-operational issue.
Please add to this discussion if you have experience in this issue. I'm assuming this is an issue that not just Konrad and I have run into.
I will add new details about this issue as I discover them.
Len
Show LessHello,
the default PDL for the demo software in CY8CKIT062BLESetupOnlyPackage_RevSE.exe is PDL3.03 (which works ).
If i use PSoC Creator 4.2 with the actual PDL 3.1.0, it will not work with these demos.
After updating the components (especially CapSense) and setting a hook at FreeRTOS it compiles and downloads without errors, but the program doesn't work on my CY8CKIT-062-BLE.
Debugging doesn't work too.
I tried the demos
"CE218136_EINK_CapSense_RTOS" and
"CE220331_BLE_UI_RTOS"
Any suggestions to solve the problem?
Best regards,
Peter
Show LessHello
I created project with PSoC Creator - FindMe example. Build passed ok , but then I failed to program the prototyping board. It asks me to upgrade the firmware with the PSoC Programmer. I go to the programmer --> Utilities, but the Upgrade firmware button is inactive.
What did I do wrong?
Thanks!
Show LessHello everybody,
Where can I find the low level drivers of the transceiver to implement a custom wireless protocol (not BLE or WiFi)?
Any documentation or example would be really useful too, if it exists...
(I wanna integrate the board in an Eclipse project with make files, so I am not using ModusToolbox)
(I got the Pionner Kit for start playing around)
Thanks!
BR
Show Less