PSoC™ 6 Forum Discussions

We started a project with the CY8C6137BZI-F34 Psoc6. We started from the mtb-example-psoc6-emwin-oled example project provided with Modustoolbox. We changed some configuration in the make file such the device in the CY8CKIT-062-WIFI-BT.mk.

We also generated a new configuration with the device configurator with the matching microcontroller.

However, we always catch Cy_SysLib_ProcessingFault() when we execute the line 2236 in the cy_syspm.c of the psoc6pdl. See the screenshot below.

I'm a bit confuse because this section on the code is only applicable  ""if curDevice == CY_SYSLIB_DEVICE_PSOC6ABLE2"". My device is not PSoC6 BLE2 device Family ID right? I feel we miss something to reconfigure for running the project on the CY8C6137BZI-F34.

Does the CYBLE-416045-EVAL support DAPLink? I want to flash it with Mbed based firwmare. The fw-loader tool always shows a timeout.

Info: Start API initialization

Info: Connected - KitProg3 CMSIS-DAP HID-061208F302098400

Info: Hardware initialization complete (515 ms)

Info: Disconnected - KitProg3 CMSIS-DAP HID-061208F302098400

Info: Connected - KitProg3 CMSIS-DAP BULK-061208F302098400

Error: Wait for device DAPLink connect is timed out

Mode switch on 'KitProg3 CMSIS-DAP HID-061208F302098400' device failed.

Thanks

I have used the Em_EEPROM on a PSoC6.

I'm trying to preload values from a struct into the Em_EEPROM at compile-time.

I've tried different methods such as "Use emulated EEPROM = No" and it isn't working.

Attached is a simple test program.

Any suggestions?

Len

Update: 01/14/2020.

Apparently when a Cy_Em_EEPROM_Read() is performed, it is pulling the data from the EEPROM image to copy into RAM from the EEPROM_addr+0x100 bytes.

Here are some code snippets as I stepped through the code from my trouble-shooting session:

cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32_t addr,  void * eepromData,  uint32_t size, cy_stc_eeprom_context_t * context)
{
  // addr = 0, eepromData = pointer to the RAM copy of the struct   size=size of the struct
     ...  //  Next curRowOffset is computed.
     curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN);  //curRowOffset = 0x100 (256 bytes) because of CY_EM_EEPROM_EEPROM_DATA_LEN.
     ...  // later the EEPROM image is copied to the RAM location.
     /* Copy the data to the user buffer */
     (void)memcpy((void *)(eeData),   // eeData = eepromData.
              (void *)(startRowAddr + curRowOffset),     // startRowAddr = 0  curRowOffset = 0x100
             numBytesToRead);
     ...  //EEPROM data 0x100 bytes into the EEPROM allocation is copied into the RAM.
}

Hi, I didn't find what I am looking for on the capsense v3 datasheet for PSoC 6.

I know how to operate individual buttons with the self and mutual configs (PSOC 6 101 helped a lot) but I need to setup a matrix with the CSX mutual config.

I am looking for a firmware example so I could try to implement it by myself. I don't know at all how similar it is to implementing a single button widget.

I am also unsure of one thing on the hardware side: as I setup the number of TX and RX pins in my capsense instance, does it refer to the amount of rows and columns, in which case a 4x4 matrix would have 16 buttons with 8 pins. I have no Idea how to read each RX row (or column) individually with the firmware I must write (maybe it's done automatically with the APIs).

Basically, I just need to know how to write code for a CSX button matrix. Thanks!

Hello,

I am currently evaluating the PSOC 6 SoC, with a CY8CPROTO-062-4343W board, for a low power Wi-FI/BT device and I have some questions regarding this chip.

- what is the release date of the PSOC 6 2M SoC (CY8C62x8/CY8C62xA) ?

I can not find the CY8C624ABZI (the one on my board) anywhere.

- which SDK should I use for Wi-Fi and Bluetooth functionnalities ?

- do you plan to port WICED on this board ? we already have the application code running on a WICED platform.

The CY8CKIT-062-WiFi-BT kit is supported, but this proto kit is not.

The main work seems to port the WWD part from the UDB SD driver (found on CY8C62x6/CY8C62x7) to the true SDHC driver (found on CY8C62x8/CY8C62xA).

As a side note, depending on the documents that we read, 5 software environnements are listed for writing code for PSOC6:

PSOC Creator, ModusToolbox 1.0, ModusToolbox 1.1, ModusToolbox 2.0, and WICED; I can also add two others, from external developpers: Amazon FreeRTOS and Mbed.

With no compatibility with each other, that is very confusing.

And, compared to WICED, there is no MTB examples to write a simple Wi-Fi application for this board that does not depend on Amazon FreeRTOS or Mbed.

Thank you.

We are looking to interface a PSOC 6 to an LTC2324-16 ADC (16 bit conversions) with a PSOC6.  The LTC2324 is a 4 channel, simultaneously sampled ADC, with an SPI interface (each ADC conversion is a 64-bit transaction).  However, to increase throughput, there are 4 simultaneous MISO outputs (slave to master data).  In this way, the ADC can send out data 4 times as fast (I.E. it has 4 "MISO lanes" to get the data out faster [4 outputs, each stream is 16 bits], as opposed to a conventional single MISO that 4 ADC results are daisy-chained to [1 output stream at 64 bits]).

Normally, stock PSOC components do not support this 4-lane MISO interface.  In order to interface this custom ADC to a PSOC6, I was going to use a regular SPI master interface with no MISO pin, and then I will make 4 digital input pins with a shift register behind each pin:

(15 D-type flip-flops per input stream) X (4 inputs) = 60 flip-flops

All flip-flops would share the common clock generated from the LTC2324.  I would then use Status registers (8 bits per status register --> 8 of them needed to read all 64 ADC bits) to get all 4 ADC results into the firmware.

--> Before I get too deep in the weeds, would this approach work?  Am I missing something?

Hello,

we are currently trying to port an audio WICED application running on 43907 to the CY8CPROTO-062-4343W board and Modustoolbox 2.0.

While the Wi-Fi part could be easily adapted, the audio part is more tricky.

The application handles full duplex audio streams through an I2S port, and unfortunately PSOC 6 SDK has no high level audio driver managing the transfer of audio periods, unlike WICED.

I just looked to port the PSOC 6 audio driver from WICED (WICED\platform\MCU\PSoC6\peripherals\platform_i2s.c, for PSOC 6 1M) but I found two annoying things:

A)

/*      * The I2S block consists of two sub-blocks:      * I2S Transmit (Tx) block: word select (tx_ws), clock (tx_sck) and data (tx_sdo) output signals.      * I2S Receive (Rx) block: word select (rx_ws), clock (rx_sck) and data (rx_sdi) input signals.      * When PSoC6 is driving both TX and RX as I2S Master, the TX and RX clock lines can be out of sync.      * If the TX/RX clock lines are connected together to an audio codec, it may not be able to output audio.      * In such settings, simultaneous RX and TX (full duplex I2S) audio can be achieved as follows:      * I2S transmitter is in slave mode.      * I2S receiver is in master mode.      * (Also note that AC spec. should be satisfied at the PSoC6 pin in order to function correctly) */

B) The copy of the audio data seems to not be performed with DMA at all, the CPU inserts each sample one at a time in the I2S FIFO:

static void service_transfer_complete( platform_i2s_direction_t dir ) {      ...     if ( num_samples > 0 )     {         samples = (uint16_t*)(&(stream->audio_buffer_ptr[stream->position + stream->data_index]));         if ( dir == PLATFORM_I2S_WRITE )         {             length = (num_samples < (I2S_TX_FIFO_SIZE - I2S_TX_FIFO_TRG_LVL)) ? num_samples : (I2S_TX_FIFO_SIZE - I2S_TX_FIFO_TRG_LVL);             while ( length > 0 )             {                 Cy_I2S_WriteTxData( i2s_base, (uint32_t)(*samples) );                 samples++;                 num_samples--;                 length--;                 stream->data_index += 2;             }         }

Does these limitations still apply to the PSOC 6 2M (found on the CY8CPROTO-062-4343W board) ?

If not, could you provide a code example to manage full duplex I2S with DMA transfers, and a higher level API than I2S PDL for PSOC 6 2M ?

Thank you.

I am migrating from the CY8KIT-062-BLE system that I used for prototyping, to making my own PCB with a PSoC6 6347BZI.  I am wanting to utilize the FSUSB component, and despite following some of the available documentation, when I check for new components I cannot see the FSUSB.  It appears in the PDL reference document (file:/C:/Program%20Files%20(x86)/Cypress/PDL/3.1.0/doc/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html  ) but does not show up when I search for new components.  Is there something I am not doing?  I restarted the system after doing all the updates and configures.

Hi Community,

After fiddling with shared memory I found my solution using pipes.

It's an easy way to communicate between cores on the PSoC6.

Problem:

I can't find any documentation or AN Aside from the CE223820 example.

I want to learn more about the usage of these pipes.