I'm using CY8CKIT-062-WIFI-BT.
If I erase the flash with Cypress Programmer and read it, I can see that the hex file is filled with 0x00.
Generally, I know that flash becomes 0xFF after erase, but PSoC6 becomes 0x00?
I wonder what (0x00 or 0xFF) to fill in the space between the booloader and the application when using the hex2bin utility.
I am using Capsense Tuner with PSoC 6 using UART. First I used the evaluation board to test. It worked fine on evaluation board using Kitprog as USB to UART convertor.
But it is not working with FTDI chip and I am always getting connection to COM Port failed.
Is it the problem of tool ?Show Less
Now, I'm using CY8CPROTO-064B0S3 to emulate our product.
I want to add some features into the bootloader and build it for CY8CPROTO-064B0S3.
However, when I refer to "supported kits" section in "PSoC™ 6 MCU: MCUboot-based basic bootloader" page, CY8CPROTO-064B0S3 seems not to be supported.
Then, is it possible to build for CY8CPROTO-064B0S3 based on mcu-tools/mcuboot.git?
What is the main advantage of having an arduino shield compatible pins along with the PSoc pioneer kit and how does it help in an application where we want to impliment several Serial Communication Blocks to interface around 14 sensors to bild an Agri station.Show Less
Where can I find more detail for selecting a MHz XTAL for Bluetooth_LE or BLE ECO for PSoC 63?
Table 58 in the CY8C63x6, CY8C63x7 datasheet identifies two oscillators for the BLE ECO input of a PSoC 63: 16 MHz and 32 MHz.
The BLE ECO appears to be the connection to the XI/XO pins referred to in Figure 5 of the same document.
There’s a single note in AN218241, PSoC 6 MCU Hardware Design Considerations regarding the BLE ECO that states: "It should be noted that the ECO available as part of the BLE radio has its own pins (XI and XO). You can add the load capacitor, crystal accuracy, and startup time details in the AltHF clock configure window as shown in Figure 9. External load capacitors for the BLE ECO are not required." Again here, it doesn't state any difference in the ECO frequency selected. Does the frequency of the crystal connected to the XI/XO pins matter as long as it matches the frequency identified in the brown box of Figure 9?
I'm trying to use the HAL System Power Management library to put the CM4 to sleep. So far, I've had no luck, and as I have found too many times, there is very little documentation available, and no examples. What documentation exists (e.g. Architecture TRM) is unclear, even suggesting that only masked interrupts can wake up a sleeping CPU.
Here's the environment:
The first problem is that the CPU either doesn't sleep, or wakes up immediately. I disable the RTOS SysTick interrupt in one of the callbacks. I also disable several other peripheral interrupts, and turn off the BLE stack, none of which has made a difference. It's likely that some interrupt is firing, but I can't think of a good way to determine which is the culprit.
The second problem is that the stated behavior, namely that the callbacks are called on wakeup (CYHAL_SYSPM_AFTER_TRANSITION) in the reverse of the order in which they are called on sleep (CYHAL_SYSPM_CB_CPU_SLEEP) does not match the observed behavior.
Callbacks are always called in the same order, even when one of the callbacks returns false in response to CYHAL_SYSPM_CHECK_READY.
Has anyone successfully used cyhal_syspm_sleep() to put one of the CPUs to sleep?
SRC_ASCLIN_ASCLIN0_RX means ASCLIN(Async/Sync serial LIN Comm) Receive Service Request.
I know that the macro is used to point at the address
0xF0038084u. But I want real time examples.
Am working on UART development on Infineon microcontroller.Show Less
I looked up the datasheets of CYB0644ABZI-S2D44 and CYS0644ABZI-S2D44.
However, I couldn't figure out the hardware difference between the two models.
I wonder if there is a separate part only for hardware other than the content that supports standard secure(S0) and secure boot(B0) respectively.
For example, I would like to know the difference between 'CYB0644A has structural differences in hardware that TM-F cannot be applied' or
'Booting sequence B0 and S0 are designed differently'.
I am using modustoolbox 2.4 with 256k flash PSoC6 controller which has CM0+ and CM4 cores. I want that cores should be deepsleep mode. I am calling
"Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT); " from CM4 core. Would CM0+ core also enters into deepsleep? I am expecting current consumption in range of 10uA, but I am measuring around ~2mA. Could you suggest?
How can can I check that CM0+ is in deepsleep or not? I also checked Switching_Power_Modes example code. I am not able to locate the main function of CM0+ core. There is only startup function as below:
Where is main function of CM0+ in Modustoolbox example code.Show Less
According to the previous post, the bin file was successfully created.
But in the following example, an error occurs when compiling.
There seems to be a problem if there are spaces in the folder, but my folder does not contain spaces.
I don't know how to solve it.