PSoC™ 6 Forum Discussions
I have a doubt regarding the use of DMA or CPU to access a UDB's accumulators:
AN82156 states "The accumulator registers operate asynchronously and may change at any time, including during CPU or
DMA accesses"
Is it safe to write into or read from the accumulators while the UDB is essentially just nop'ing around? I'd like to use D0 and D1 for static parameters used to process A0 and A1.
Show LessIn the PSoC6 Programming Specifications (Rev L), Section 5, "Step 1.A Acquire Chip" pseudocode there is a step to set the TEST_MODE bit in the TST_MODE_SRSS register.
// Enter CPU into Test Mode
// Set TEST_MODE bit in TST_MODE SRSS register
WriteIO (SRSS_TST_MODE, SRSS_TST_MODE_TEST_MODE_MSK);
Later this bit is checked:
// Check TEST_MODE bit is set
ReadIO (SRSS_TST_MODE, OUT dataOut); if ((dataOut & SRSS_TST_MODE_TEST_MODE_MSK) == 0) return FAIL;
I can find no details about where this SRSS_TST_MODE (or TST_MODE_SRSS) register is located, or how to construct the SRSS_TST_MODE_TEST_MODE_MSK mask.
The only lead I've found is that the PSoC4 had SRSS (System Resource) registers, it appears.
I have didn't see anything related in the PSoC 63 Architecture TRM, nor in the Register TRM. Searching the broader internet, and ARM resources have not helped so far.
- What are the address and definition for the TEST_MODE bit and the register that contains it?
- In what reference will I find this information?
I am doing product development on PSoC63.
I am looking for a test firmware to obtain CE and FCC RF certification.
I was provided with the attached firmware by Cypress when I was developing my product with PSoC4.
Do you offer similar firmware for PSoC63?
Best regards.
Show LessI'm working through the PSoC 6 MCU Programming Specifications (Rev-L), adapting the PSoC4 HSSP example for the PSoC 6.
I am looking for help related to the SWD_Write() and SWD_Read() implementation.
The details of these functions are not included in the psuedo code, only a quick summary in Table 4-1:
Header 1 | Header 2 | Header 3 |
---|---|---|
SWD_Write | IN APnDP, IN addr, IN data32, OUT ack | Sends a 32-bit data to the specified register of the DAP using SWD interface. The register is defined by the “APnDP” (1 bit) and “addr” (2 bit) parameters. The DAP returns a 3-bit status in “ack”. |
SWD_Read | IN APnDP, IN addr, OUT data32, OUT ack, OUT parity | Reads 32-bit data from the specified register of the DAP using SWD interface. The register is defined by the “APnDP” (1 bit) and “addr” (2 bit) parameters. DAP returns a 32-bit data, status, and parity (control) bit of the read 32-bit word. |
I do not see where the actual values that SWD_Write() and SWD_Read come from for these registers.
- What values should I use for these macros, or where can I find this information clearly?
- When I look at the PSoC 4 HSSP code example, I don't see a clear mapping between the APnDP and Address values given in the PSoC6 Programming Spec and the values used for the PSoC 4 HSSP examples.
Macro Name Used in PSoC6 Programming Specs |
---|
IDCODE |
ABORT |
CTRL/STAT |
SELECT |
RDBUFF |
CSW |
TAR |
DRW |
I am trying to program the CY8CKIT-062-WIFI-BT kit using the KitProg from a CY8CKIT-059 PSoC 5LP Kit. The Kitprog has been separated from the PSoC 5LP stick. I am not using the WIFI-BT Kit's own Kitprog.
I am able to program the CY8CKIT-062-WIFI-BT successfully with a MiniProg4.
When trying to connect with the 5LP KitProg (v2.21), I receive the error "Given Target Method (6) is not supported!"
This error is not in the help manual.
- What does it mean?
- What is "Target Method (6)?"
The I2C master mode is being used in a project to communicate with a FRAM chip and an IMU chip. Communication has been going successfully but there seems to be a problem with the I2C and SDA pin pull-down power when a communication is first started. Attached is a trace of the start of a 4 byte write to the FRAM. The top trace is of the SCL pin and the bottom trace is of the SDA pin. Note that on the first few pulses, neither the SCL or SDA pins are pulled close enough to ground for the FRAM to recognize them.
The PSoC 6 I2C component is configured as a master at 400 kbps with TX and RX FIFO. Both SCL and SDA pins are configured as bidirectional with Open drain, drives Low and the initial state is High.
Note that on the first try neither the SCL or SDA lines are pulled down but not completely to ground. Note also the exponential decay for both the pull-down and for the pull-up, particularly on the SCL trace. The FRAM does not respond; so the transmission is aborted. Then, about 30 microseconds later, the transmission is again started. This time the pull-downs and pull-ups are normal and the transmission is completed successfully. Afterwards a read of the FRAM locations was done to verify that the information was properly written. This test was repeated every second and the same traces resulted.
A second trace which zooms in on the first aborted transmission is also included.
What could be the problem and how could it be avoided?
Show LessDear,
We are trying to build a Radial Slider demo on PSoC MCU.
Does Cypress have related evaluation board and sample code?
Thanks!
Best regards,
Lei
Show LessI am developing a product using the BLE module (CYBLE-416045-02) of PSoC 63.
The base firmware is CE222802, a sample project.This project is divided into two projects, and "CE222802_Bootloader_Encrypted_App0.cydsn" plays the role of Bootloader.
When I use "PSoC Programmer" to program the firmware built in the Bootloader project to a new BLE module, at first glance it looks like that I succeed to write it without an error, but it is not actually written.
However, when I use "PSoC Creator", I can program it and also it is written successfully.
Strangely enough, when I program it with "PSoC Creator" at first, I can program it with "PSoC Programmer" without an error after the second time.
Is it possible to program by using "PSoC Programmer"? If so, please tell me how to program it.
------------------------------
PSoC63のBLEモジュール(CYBLE-416045-02)を使用して製品を開発しています。Show Less
ベースとなっているファームウェアはCE222802というサンプルプロジェクトです。このプロジェクトは2つのプロジェクトに分かれており、「CE222802_Bootloader_Encrypted_App0.cydsn」
のほうがBootloaderの役割を担っています。
Bootloaderのほうのプロジェクトでビルドしたファームウェアを「PSoC Programmer」を使用して新品のBLEモジュールにプログラムしたところ、エラーは発生せずに正常
に書き込みができたように見えるのですが、実際には書き込めていません。
これに対して「PSoC Creator」からプログラムすると正常に書き込めます。
また、「PSoC Creator」で一度プログラムすると、それ以降は「PSoC Programmer」でプログラムが出来るようになります。
新品のBLEモジュールに「PSoC Programmer」からのプログラムが出来ないのは仕様なのでしょうか?
I am trying to set up Bluetooth LE pairing using Authenticated LE Secure pairing with encryption and Numeric Comparison. In the generic BLE event handler, I can get to:
case CY_BLE_EVT_GAP_NUMERIC_COMPARISON_REQUEST:
BLE_PRINTF("Compare this passkey with the one displayed in your peer device and press 'y' or 'n':"
" %6.6lu \r\n", *(uint32_t *)eventParam);
It is fairly obvious that I should insert my own application specific code at this point to present the question to the user in way that is supported on my system. And I can handle that.
However, what is NOT obvious to me is how I am supposed to acknowledge the user's confirmation that the pairing should proceed. It seems like there should be some predefined CY_BLE function to call, but I can't locate it.
Anybody know how to complete the Numeric Comparison?
Thanks,
Ed h.
Show LessAs PSoc6 does not have a glitch filter component, can anyone let me know the alternatives?