PSoC™ 6 Forum Discussions

I have the PSoC 6 connected to four MX25(https://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf )external flash chips over SPI.

When I connect any one, or two chips to the psoc I can read and write great. When I connect 3 or more I am unable to read or write any data to any of them. Everything shows up incorrectly.

Any idea what could be causing this? I have tried adding pull up resistors to the chip selects. Also all of the chips work separately, and work in any combination of two.

Hi,

I'm trying to use 400kbps as desired data rate for my I2C component, but only to discover that the SCB clock (kHz) generated by PSoC Creator itself is set to 7500, which apparently to be out of range. Is there anyway to help understand how this clock value is generated while I'm not using external clock terminal?

Thanks!

Best,

Joseph

Are there specific DC-DC power interface or ESD protection circuits from Infineon that pair well with PSoC 6?

I'm interested in design examples or reference designs that pair PSoC 6 with Infineon power components or sensors.

Greg

I'm trying to achieve the following:

One component in my design outputs a trigger signal. On each positive edge of this output, I'd like use one DMA channel to do the following things:

- Transfer one halfword from the SAR ADC to a 16-bit UDB

- Transfer one word from a timer to a memory location (uint32_t)

- when both are done, the DMA channel should generate one output trigger that is routed into the UDB.

I connected the DMA channel's trigger input and output to a scope.  I can see the input triggers, but the output is silent. These are my descriptors:

My guess is that, since descr_timer is chained back to descr_adc, an endless loop is created and no trigger is generated because the entire (endless) chain is never completed. However, I've tried many other combinations of settings and none of them had the desired result.

I've also attached the current state of the whole project (the DMA component in question is in the top level design).

I'm thinking about handling DMA errors with the DMA's interrupt. It would be triggered only on errors, not on channel completion. Any advice on this is appreciated, but not the main point of this question.

The attached project contains of

• the SAR ADC with one analog MUX for each input
• an 8-bit datapath with parallel out that selects the analog MUX inputs
• a state machine to cycle through 4 analog result destinations, which are served by
• 4 DMA channels.

It uses a tremendous number of PLDs (12 of 24). Why is that so and how can I reduce the amount of used resources?

The idea behind the datapath is as follows:

It's supposed to work like a 4:1 memory-to-routing mux. It has a sel[1:0] input that is routed to the instruction select inputs[1:0]. The selected instruction loads from F0, F1, D0 or D1 to an accumulator, which is then output via the parallel bus. That way I can preset channels in software and select them with the sel[1:0] lines when appropriate. The ADC result is then copied to the correct destination with the selected DMA channel.

hi，I have downloaded BLE APP "CySmart_Android_1.2.0.156_Source_Code_0" in my Android phone that IOS version is Andriod 10,but I can't find install file(.apk) in my phone ,so i don't know how to install it, could you tell me what's problem or send me a new APP install package?Thanks!

Our application consists of a main app and a bootloader/DFU.

We are using the watchdog timer in the main app. When the watchdog causes a reset, we get stuck in the bootloader/DFU unless the WDT_RESET bit is cleared in RES_CAUSE register by either

SRSS_RES_CAUSE = 0x00000001U;

or

Cy_SysLib_ClearResetReason();

I inspected the code and found that the bootloader/DFU goes all the way into Cy_DFU_ExecuteApp, sets the app ID and calls CySoftwareReset. But if the WDT_RESET bit is set, it always "wakes up" as the bootloader/DFU.

Is that intentional or have I missed something? I was hoping that we didn't have to deal with the watchdog in the bootloader/DFU, and could clear the bit in the main app.

hi，我有购买一套“ CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit”，配套的capsense的代码是基free os的参考代码，我现在

想单独学习capsense功能，单独建立了一个不跑OS的capsense工程，基本与基于free os的参考代码一致，只是没有使用Free os，

实际bug发现，代码在CapSense_Start就过不去，具体是卡在uint32 CapSense_IsBusy(void)里，请教一下这是什么问题？或者有没有

不基于OS的capsense示例代码？谢谢！