PSoC™ 6 Forum Discussions
I have a simple program for reading the JEDEC information from a serial flash chip using the low-level API.
static void SPI_FlashWriteByte(uint8_t byte)
{
SPI_ClearRxFifo();
SPI_Write(byte);
while (SPI_GetNumInRxFifo() == 0);
SPI_ClearRxFifo();
}
static uint8_t SPI_FlashReadByte()
{
SPI_ClearRxFifo();
SPI_Write(0xFF);
while (SPI_GetNumInRxFifo() == 0);
return SPI_Read();
}
static void SPI_FlashReadJEDEC_Info(uint8_t* mfgID, uint8_t* memoryType, uint8_t* capacityID)
{
CS_FlashEnable();
SPI_FlashWriteByte(0x9F);
*mfgID = SPI_FlashReadByte();
*memoryType = SPI_FlashReadByte();
*capacityID = SPI_FlashReadByte();
CS_FlashDisable();
}
int main(void)
{
__enable_irq(); /* Enable global interrupts. */
Cy_SCB_SPI_Init(SPI_HW, &SPI_config, NULL);
Cy_SCB_SPI_Enable(SPI_HW);
Trace_Init();
Trace_Log("\033[2J\033[H"); // Clear screen
Trace_Log("SPI Test\r\n");
for(;;)
{
uint8_t mfgID, memoryType, capacityID;
SPI_FlashReadJEDEC_Info(&mfgID, &memoryType, &capacityID);
Trace_Info("MfgID: 0x%02X, memoryType: 0x%02X, capacityID: 0x%02X", mfgID, memoryType, capacityID);
CyDelay(100);
}
}
Which produces the following signals.
D0 = chip select
D1 = SCLK
D2 = MOSI
D3 = MISO (the decoded data at the top is from MISO)
The problem is that each SPI_FlashReadByte() call returns the value that was in the FIFO from the SPI_FlashWriteByte() call.
I've tried using the high-level API with the same results.
Show LessI need to be absolutely certain of the following: My hardware engineer asked me to verify:
P10_0 can be configured A to D
P11_2 thru P11_6 can be configured to SDIO bus on MCU
P12_0 thru P12_3 can be configured to SDIO bus on MCU
P13_0 thru P13_2 can be configured to SPI bus on MCU
P4_0 thru P4_1 can be configured to I2C on MCU
I cannot find the SDIO in reference manual, datasheet, and trouble understanding 002-18449_002-18449_Alternate_Functions.xlsx and 002-23185-CY8C62x8_CY8C62xA_Pin_Functions_1_1.xlsx
Having trouble making certain without a doubt. Please direct me to documentation that will satisfy and prove to me that the above will work for his design.
Thank you.
William
Show LessI'm looking for ways to ease the chip from some combinatorial logic. I have 4 instances of a component that has a 4-input OR gate, and I'm tempted to remove that OR gate by moving it into a datapath. I'd use parallel in, and use the all-zero detector (inverted) to see if any bit is set - if that is feasible at all. Would that use less PLD resources than a 4-input OR gate? the number of signals (4 in, 1 out) is the same, but does it "free the way" for other parts of a larger design?
Also, could this be combined with a memory-to-hardware latch (D register to accumulator to parallel out)?
Show LessHello,
I am reading AN22875 ”DMA on PSoC 6 MCU”. So, I have a question about "Elements of a Transfer" in section 10.1 and Table 1.
Although it is written as 2 cycles in the explanation, it is 3 cycles in the table. Is this right?
The explanation:
A transfer can be split into multiple operations as shown in Table 1 with the corresponding cycles needed for their execution. Each transaction is initiated by a trigger, which goes through trigger synchronization circuit and takes up two cycles. These two cycles will be consumed whenever there is a trigger event being used.
Table 1:
Operation | Cycles (Slow Clock Cycles) |
---|---|
Trigger Synchronization and Priority decoding | 3 |
Start state machine and load channel config | 3 |
Load descriptors | 4 for single transfer 5 for 1D transfer 6 for 2D transfer |
Load next pointer 1 | 1 |
Moving data from source to destination | 3 |
Thanks,
Kenshow
Show LessHi
Is there a specific programming sequence for writing firware to CYBLE-416045-02 to program bluetooth? If so, where can I find it? Can it be programmed over the SWD interface in PSoC Programmer or Creator?
Thank you
Show LessI'm working with Mbed Studio 6.1 and CY8CPROTO-062-4343W on a project with MBed OS 6.2
Following the sample code of the HAL documentation I created the following functions:
#include "cyhal.h"
#include "displayThread.h"
bool timer_interrupt_flag = false;
cyhal_timer_t timer_obj;
static void isr_timer(void *callback_arg, cyhal_timer_event_t event)
{
(void) callback_arg;
(void) event;
/* Set the interrupt flag and process it from the application */
timer_interrupt_flag = true;
displaySendUpdateTime();
}
cy_rslt_t initPeriodicTimer()
{
cy_rslt_t rslt;
const cyhal_timer_cfg_t timer_cfg =
{
.compare_value = 0, /* Timer compare value, not used */
.period = 999, /* Defines the timer period */
.direction = CYHAL_TIMER_DIR_UP, /* Timer counts up */
.is_compare = false, /* Don't use compare mode */
.is_continuous = true, /* Run the timer indefinitely */
.value = 0 /* Initial value of counter */
};
/* Initialize the timer object. Does not use pin output ('pin' is NC) and
* does not use a pre-configured clock source ('clk' is NULL). */
rslt = cyhal_timer_init(&timer_obj, NC, NULL);
if ( rslt == CY_RSLT_SUCCESS)
{
/* Apply timer configuration such as period, count direction, run mode, etc. */
rslt = cyhal_timer_configure(&timer_obj, &timer_cfg);
if ( rslt == CY_RSLT_SUCCESS)
{
rslt = cyhal_timer_set_frequency(&timer_obj, 1000);
/* Start the timer with the configured settings */
if ( rslt == CY_RSLT_SUCCESS)
{
/* Assign the ISR to execute on timer interrupt */
cyhal_timer_register_callback(&timer_obj, isr_timer, NULL);
/* Set the event on which timer interrupt occurs and enable it */
cyhal_timer_enable_event(&timer_obj, CYHAL_TIMER_IRQ_TERMINAL_COUNT, 3, true);
rslt = cyhal_timer_start(&timer_obj);
}
}
}
return rslt;
}
When compiling the project I get the following 2 errors (timerISR.cpp is my function above):
[Error] @0,0: L6218E: Undefined symbol cyhal_tcpwm_enable_event(TCPWM_V1_Type*, cyhal_resource_inst_t*, unsigned, unsigned char, bool) (referred from BUILD/CY8CPROTO_062_4343W/ARMC6/timerISR.o).
[Error] @0,0: L6218E: Undefined symbol cyhal_tcpwm_register_callback(cyhal_resource_inst_t*, void(*)(), void*) (referred from BUILD/CY8CPROTO_062_4343W/ARMC6/timerISR.o).
but I can't find the ultimate ..internal() targets anywhere...
Hi,
I'm implementing a solution to KBA229335 where I replace cy_syspm.c in a pre-build instruction.
However, I'd like to remove this fix when the PDL is updated, thus I would add a precompiler check in cy_syspm.c for the PDL version.
Is there such a macro? Something like:
Show Less#define PDL_MAJOR (3)
#define PDL_MINOR (1)
#define PDL_MICRO (2)
Hello
I want to know if a special saving method is possible in PSoC6.
First, a header is created each time the data obtained from the sensor is recorded.Write multiple pieces of information there.
EX)
●header A ●header B
-Data A-1 -Data B-1
-Data A-2 -Data B-2
When reading, I want to collect these data collectively using the header as a mark.
I would like to know how if this is possible.
Header information
●Recording start date and time
●Setting infomation
Data Infomation
●Recording date and time
●Recorded sensor data
Best Regards
Hayato
Show LessHello,
I used the example code PSoC 6 MCU VDAC Sine Wave Generator Using DMA with the CYBLE-416045-EVAL EZ-BLE. It does create a sine wave, and I can control the frequency by controlling the clock divider with "Clock_1_SetDivider(Clk_Divide);" where Clk_divide is 16 or greater. However when Clk_divide is 16 the sine wave is supposed to be 5kHz but it is only around 3.8kHz. Oddly enough if the Clk_Divide is 19 the sine wave is higher frequency (around 4.2 kHz). Let me know if I need to clarify anything or add the code I used to cycle through frequencies.
Thank you,
Kyle Weeks
Show LessAccording to Application note AN73617 https://www.cypress.com/documentation/application-notes/an73617-psoc-designer-boot-process-reset-main
There are 4 times involved in the startup of the processor:
When measuring signals on the CYCKIT-62 BLE developer kit, I got the following result:
P13_7 is a pin configured as an output, which is controlled by software: On main start, a startup signature is generated, to identify main has started. It is also set high during the execution of the ADC isr, which means it is able to identify when the fist sample (after boot up) is taken.
Reset is the reset pint status
VProcessor is measured on the BLE power monitor jumper J8.
On a cold boot Vprocessor (red line) rises and is stable for about 7..8ms. Then is trails off slowly to about half the supply Voltage. The reset pin actually follows the same behavior, but I have shown the digital interpretation here. Clear is that when reset goes low, the decline of Vprocessor is much slower, likely because the processor is halted.
Interesting is to see the behavior of output pin P13_7: After 11 ms of high it goes low for about the same time. Then the main start signature is identified (high) followed by the hardware initialization (ADC) and the triggering of the ADC ISR. after a short amount of samples, reset goes low and the processor stops executing.
Reset is kept low (probably by kitprog 3) for about 200ms, after which the power to the processor is raised (to 3.3V) and shortly after the reset follows. This time the output of P13_7 stays high until the main (and later the sampling) starts.
Questions:
1. Output behavior of P13_7 is different on cold boot. Is that due to the fact that the power supply is not stable?
2. Does the timing specified in a the Application note still apply for the PSOC6 ?
3. Testing with different clock settings ( which should impact T3 and T4, but not T2) I estimate T2 to be around 21ms, which seems to occur after every reset. Keeping the device in reset is therefore not an option when fast response times are required. Would waking up from hibernate eliminate these 21ms and (potentially) allow faster startup-times (with responses within 10ms are required)?
Show Less