PSoC™ 6 Forum Discussions

Hi Everyone,

I am currently programming on PSOC CY8C6137BZI-F54 . My majority work is for the analog DAC and current source. I tried making the schematic attached with this post. While building the code I receive the error mentioned below.

"Net "Net_261" is connected to analog mux "AMux_3" and analog mux "AMux_2", but it may connect to only one analog mux when it is an analog mux common connection."

Also I wanted to ask the analog multiplexer can also work as de-multiplexer? Please help me on this.

Hello,

I'm a college student using a Cypress CY8CPROTO-063-BLE (PSoC6) board for a course, this is my first time working with this board. I was trying to use the board for the first time to run a Hello World example, and opened PSoC6 creator inside my Windows 10 VM, running on my MacBook.

PSoC6 creator said it expected a firmware of 1.01, while the board firmware was 1.05, and said to update through PSoC6 Programmer. Thus, I opened the programmer (while keeping the creator open, which I later learned I'm not supposed to do), and tried to updating firmware. The first few times I tried update, the VM software would prompt me as to whether I want to connect the board & bootloader to Mac or Windows, which would cause an error before the upgrade began, with a pop up saying the boot loader was not recognized. I then marked the prompt to always connect to Widows without asking, and tried updating again. This time, the update began successfully, with a green bar appearing, but then a pop up said the boottloader was not recognized again, and the update failed again.

After this, the board was no longer recognized by the programmer, and no longer appears in device manager. I've tried unplugging a number of times, restarting Windows on the VM, and even holding the reset button for ten seconds as was recommended somewhere. The device simply doesn't appear in device manager anymore (it appeared under USB as COM3 before the failed update). MacOS also doesn't recognize the device. Note that the orange status LED2 by the microUSB is still flashing quickly, as it was before the update failed, and the orange power LED1 is still solid. A green LED was on before and after the update failed, including when I was trying to fix this and tried to reset it, but right now while I am writing this post, that LED is now off for some reason.

I'm honestly very lost at the moment. I'm in touch with my professor regarding acquiring a new PSoC6 board, but if anyone knows how I could fix this, it would be extremely appreciated.

Hi.

My project uses a PSoC 6 to drive an external ADC device. The ADC requires a clock source, and I'm using the PSoC 6 to generate that clock via a PLL and the one CLK_HFn clock source that can be connected to an external pin (CLK_HF5 on the CY8CPROTO-062-4343W). This works well, except that we also want to drive the PSoC 6 from an external VCTCXO clock source on EXTCLK.

When I enable EXTCLK, though, the Device Configurator will no longer allow me to select an output pin for my ADC clock.

Is it possible to have both an external clock input (on EXTCLK) and and external clock output in the same design?

Thanks,

-Nick

I connected a PDM Mic(IM69D120) with my PSoC6, I want to save the PCM data to RAM by DMA, and I use the sample code CE220762,

but I found when I cutoff the power supply of MIC, and there was no data on PDM Data line, but DMA could still get the data from RX_FIFO_RD,

Why the PDM data line no data but DMA can still get the data from RX_FIFO_RD?

Hardware:PSoC63

Software:CE220762 – PSoC 6 MCU PDM to I2S Example

Mic:infineon  IM69D120

Dear Cypress,

One of my customer has been developing their product using PSoC 6 (CY8C6136BZI-F14).

Their product will use both USB and I2S and they want to run CM4 as fast as possible.

To support Audio frequency of 48kHz and 44.1kHz, they are planning to feed 34.4064MHz to ECO.

They will generate 147.456MHz clock using PLL and for the USB clock they are planning to feed 48MHz to External Clock.

But when I tested with PSoC Creator, the maximum frequency I could feed to ECO was 33.3MHz.

Meantime in the data sheet the maximum frequency of ECO source is stated as 35MHz.

The customer also confirmed this using MTB 2.2.

But to stay in the safer side, they want to confirm/ask the following questions.

Question 1.

Can the customer feed 34.4064MHz as the source of ECO?

Or is/are there limitation that ECO can accept only up to 33.3MHz?

Question 2.

How much diffusion between I2S clock and USB Audio is allowed?

Can it be in the order of 0.1% or 0.01%?

Best Regards,

28-Oct-2020

Motoo Tanaka

I am developing BLE devices using PSoC63.

I have created a project with BLE components in place using PSoC Creator.

I would like to export this project to EWARM.

PSoC Creator generates an archive file of the BLE stack when you use BLE components.

Can I use this archive file when I export to EWARM?

Best regards.

Hello,

We need to pre-program Sflash before programming the application to PSoC6.

If we need to write 64 bytes of hex value such as "cdaa5e5bbc31ed47b9e1f5b07b919815c2e1dde780d9b4701c01f812cad407ef"

Is there any command can write hex value into entire Sflash row?

I have studied "Cypress Programmer 2.1 OpenOCD" but there's only write 4 bytes at one time

./openocd.exe -s ../scripts -f ../scripts/interface/kitprog3.cfg -f ../scripts/target/psoc6.cfg -c "init; reset init; flash fillw 0x16000800 0xcdaa5e5b 4; shutdown"

If I write next 4 bytes into next offset 0x16000900:

./openocd.exe -s ../scripts -f ../scripts/interface/kitprog3.cfg -f ../scripts/target/psoc6.cfg -c "init; reset init; flash fillw 0x16000800 0xcdaa5e5b 4; shutdown"

The previous value would be earsed.

Below is the way I used to read value form Sflash in my application:

uint8_t otp_key1[4] = {0};

uint8_t otp_key2[4] = {0};

emcpy(otp_key1, (const void *)0x16000800, 4);

memcpy(otp_key2, (const void *)0x16000900, 4);

Please correct me and help if my way is suitable.

Thanks.

BR,

Wayne

If I understand correctly, there are two interfaces to Cy_SCB_SPI, the high-level interface which permits concurrent reads and writes but is asynchronous / interrupt driven, and the low-level interface which permits only reads or writes but allows you to choose asynchronous or blocking.

I'm wrapping the Cypress SPI interface for calling code that expects a blocking SPI read+write function that starts communication immediately (the talk of FIFOs in the documentation makes me worry that sometimes the transfer is simply queued for later), and power usage I'd like to put the core to sleep until the interrupt indicating the transfer is complete (or other SPI state change) and for performance I'd like to avoid timeouts (either sleeping longer than needed or waking up too soon).

I thought it was possible to build a blocking interface on top of Cy_SCB_SPI_Transfer where my interrupt handler sets a flag indicating that the transfer is done, but I'm encountering a race condition where the interrupt handler runs between the point where I check the flag and where I sleep for the next interrupt, leading to my core sleeping forever as no further interrupt arrives.

I've also looked into building it on the low-level interface with Cy_SCB_SPI_Read and Cy_SCB_SPI_Write but these appear to just block until data is in the FIFO not until the communication is actually complete over the wire. See Re: Cy_SCB_SPI_ReadArray documentation  and Re: Use Low Level SPI read .

Is there any way to do build a blocking full-duplex SPI function? Have I overlooked something in the API?

My device is SPI master.