PSoC™ 6 Forum Discussions

Hi everybody. Hi have made my own board with CYBLE-416045-02. I have put on V_Backup pin a 3V battery. When I remove VDD (in the schematic VCC_3.3_CYBLE) RTC resets to the last saved datetime. Can You help me? Thanks. In the follow I have attached the piece schematic and the init code of rtc

void init_rtc(void){
cyhal_rtc_init(&my_rtc);
}

I'm currently finalizing a hardware design using the PScC6 Creator module and want to know if any of the available IO pins can be used to wake the PSoC6 out of deep sleep or hibernate mode? Currently, I have a push-button connected to pin P9.2, which will ground it when pressed. My idea is to include a denounce circuit inside the PSoC6 (based on this app note here) and wake it from the lowest possible sleep mode. Are there any other things I need to consider for this use case?

Thanks!

Jason O

Hello all,

I am currently using a psoc CY8C6347BZI-BLD53 to do some very high speed SPI transfers at 25MHz and have come across some interesting behavior of the SPI FIFO. 

Initially I was using the Cy_SCB_SPI_Write() to fill the FIFO to 64 with uint16_t values that is triggered when the FIFO reached a value of 8. Upon further investigation with an oscilloscope there was some delay between transfers  (~570ns) and a larger delay (~972ns) between them when writing to the FIFO during an interrupt using that api.

The delay between each message becomes one clock cycle consistently when using Cy_SCB_WriteTxFifo() even while writing to the FIFO which solves my timing critical problem. However, I now begin to receive the interrupt after ~30 values being transferred, which means the FIFO isn't being fully filled to the value of 64 (i'm guessing ~38) . I found that if I add a delay of ~20 cycles after each call of Cy_SCB_WriteTxFifo() the right number of data (54) can be seen transferring on the oscilloscope before the next interrupt occurs.

I am reaching out for some help with trying to eliminate the added delay cycles after each Cy_SCB_WriteTxFifo, or at least to understand the root cause of why it work when they're there. I have looked into the TRM for the architecture, but they do not go into detail about FIFO operation. I don't have a usb right now so I can't post images from my oscilloscope but if you need them to understand I should have one by this Monday.

Your help is greatly appreciated!

How does the Pipes IPC library know the size of a message sent through a pipe?

The CE223820_IPC_Pipes01 sample project gives a nice example of usage but the notion of message size if absent. Is the message size fixed at 256 payload bytes as the example presents? If not, how is message size configured?

Thanks - JJS

I would like to be able to interact with bleuio device (central) but still maintain the capability of interacting with the standard service provided for cypress devices.  When I scan the parameters for the bleuio/dialog device with my smart phone, this is what I get:  

For me to be able to interact with this central device, is it as simple as assigning service uuid as a secondary;

and then correspondingly setting read and write characteristics (of which I do not see any secondary fields)

Or do I add another custom service (say Server_UART2) on top of the original and enter in the respective values?

Alright, tested the latter case and that does not seem to work, and based upon description a secondary service think this will not work as well.  What am I missing to be able to communicate with this other device?  Thanks

I'm currently working on a custom design that utilizes the PSoC6 EZ Creator Module. My application uses a digital microphone with I2S support and I am just wondering if there the SCK, WS, and SD pins for the I2S bus can be routed to any of the available IO pins on the module, or if there are certain ones I should connect to?