PSoC™ 6 Forum Discussions
Hi,
I am using Toshiba NAND flash with CY8CKIT-062S2-43012. I am using this flash for OTA using HTTP with the sample application. The bin file is downloaded to NAND flash. The download is successful. After the download the board reboots and reads magic number, swap_type, image_ok flag and copy_done flag. The function boot_write_copy_done() is supposed to write the copy_done flag. Can you tell me where is it getting called in the flow?
Reboot happens after OTA and then it results in following error:
[ERR] ********No bootable image in slot
Please find the attached screen shot
Should I update any variable in the code, so that the bootloader should look for image in the Toshiba NAND flash instead of the default QSPI NOR flash?
Also please tell me the steps carried out during validation of image in secondary slot. Do you have any documents or links regarding this?
Any information will be of great help.
Thanks,
Binsy M S
Show LessOriginally, there was no problem. Suddenly, the code could not be downloaded. The following is info:
Started by GNU MCU Eclipse
Open On-Chip Debugger 0.10.0+dev-4.1.0.1058 (2020-08-11-03:47)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
adapter speed: 2000 kHz
adapter srst delay: 25
adapter srst pulse_width: 25
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
cortex_m reset_config sysresetreq
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.21.1005
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 3.328 V
Info : kitprog3: acquiring the device...
Error: kitprog3: failed to acquire the device
Info : clock speed 2000 kHz
Error: DAP 'psoc6.cpu' initialization failed (check connection, power, etc.)
Info : psoc6.dap: powering down debug domain...
Warn : Failed to power down Debug Domains
Hi,
Currently I am testing aws_demos example in ModusToolbox2.2.
When I was using CY8CPROTO-062-4343W Rev06(IC marked with A33), I am able to reprogram and switch between different projects.
But when I changed to CY8CPROTO-062-4343W Rev08(IC marked with B33), I only programmed once and it seems the program had not been properly flashed into the board. The debug port was totally shut down and I cannot reprogram any more.
Even when I pressed SW3 to switch mode, also can not do it. It will go back to "KitProg3 CMSIS-DAP" in device manager. Please refer to the attached picture. I already killed several Rev08 boards when I was trying to program aws_demos into these Rev08 Boards.
Below is the log from Cypress Programmer when I'm trying to connect.
Please help to analyze and debug. Thank you very much.
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I am using the CY8CKIT-062-Wifi-BT Pioneer kit which comes with the CCG3 Type-C controller. By default, the Type-C connection acts as a PD power source.
I would like to know how to control CCG3 controller using Modustoolbox. To be more specific, I would like to have some reference source code that is able to control the CCG3 as and when it will supply power to another PD device.
Can you show me any reference code, library or HAL that communicate with the CCG3 controller in Modustoolbox environment?
Thanks.
Show LessHi,
One of my customer wants to measure time between external IRQ signal,
which is supposed to be about 1ms.
So I tried with the following schematic using CY8CKIT-062-BLE.
Note: Counter_2 is used to generate dummy IRQ signal generator.
And Tera Term output seems to be OK,
Note : I'm changing the interval by 1 in the firmware loop.
But the customer is anxious if triggering both reload and capture with same edge could cause wrong sequence,
for example, if there is/are chance that the captured value is the reload(ed) value (aka 0).
IMHO, if TCPWM was designed in usual sync manner,
the following two will take place at the same time,
so captured value won't be overwritten with the reload value.
(1) Counter Value -> Capture Value
(2) 0 -> Counter Value
Question: Is my assumption correct?
Or is/are there something I need to be aware of to do this measurement?
My test project is attached.
moto
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Hello everyone,
I'm working on a project that involves a legacy ASIC that requires an external DMA controller with full DREQ/DACK mechanism. Unfortunately, non of the microcontrollers available today provide that type of DMA. Well, I'm talking here about a fully fledged DMA controller similar in signaling and behavior to that of Intel's 8237. Bitbanging, playing with address bits/signals of FMC or any workaround is not acceptable for me.
Recently, I got some suggestions to implement it using a CPLD or FPGA, but I've never used one in any of my designs. Someone also referred me to PSoC series, but not sure whether I can achieve what I want using the Logic Array embedded in that SoC.
Any feedback is highly appreciated!
Zaher
Show LessI have a problem with saving bonding data. When I bond with a peer device I get the CY_BLE_EVT_PENDING_FLASH_WRITE event. Then I try to save the data in Flash using the Cy_BLE_StoreBondingData API. Unfortunately, every time I call this function I have a hard-fault (especially due to the call of Cy_BLE_StoreStackData) ... I can't understand what the problem could be. Has anyone had this problem?
Show LessI'm still working on trying to get my DFU working on a CYBLE-416045-02 module. The system seems to work with CySmart all the way up to when the newly downloaded program is supposed to start. I have traced it through the boot loader to where it is supposed to start APP1, but then the program goes to la-la land, never to return.
The attached code is a stripped down version of my real code (which is much much larger). But it still has the ram and rom allocations in the dfu_cm*.ld files that my real program uses. I suspect that I have something slightly wrong in those files, but as best I can tell they seem to be correct for my code which needs much more room than the default ram and rom allocations.
I have been trying to get this to work off and on for several months now without success and I am now starting to get desperate. If anybody can spot the error that is killing me I will be greatly in his/her debt.
Ed H.
Show LessHallo Cypress community,
we have been coding on the CY8KIT-062-BLE before and have some extensive designs running. Now we want to
deploy this code to the new CY8KIT-062 WiFi-BT. We understand that for the wifi coding the tool to use is the
wiced studio. Can we migrate the entire designs to the WICED Studio ? If not, how can the WICED Studio designs / code be joined with the code from the PSoC Creator ? Are the firmware uploads independent i.e. the WICED upload only programs the WiFi component ? If so, how to exchange data from both code bases ?
Any help / quick start on this is greatly appreciated.
Regards
Stefan
Show LessHello,
I'm new in Bluetooth.
I try to run Bluetooth Mouse HID Example on kit CY8CPROTO-063-BLE.
- I create new project
- I select target device to CYBLE-416045-02
- I click update components
- I set ports for leds 7.1 7.2 6.3
- I bulid project and program both cores one by one CM0 and then CM4
After that I try to connect to BLE HID Mouse ( it is discoverable by my android phone)
Problem is that: phone can't connect by bluetooth to mouse .
Is anyone knows. What I have to change in example project to makes it work, or what I can do wrong?
( For bluetooth 4.1 and other kit it works fine)
I will be very thankfull for help.
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