Recent discussions
Is it possible to use the digital mux pins to make USB work on the
CYBLE-416045-02 |
module? If not, is there another module with USB functionality?
Show LessHi There!
Please refer to the below opp number and customer requested CY8C6316BZIBLF54 Datasheet.
I will PM the internal Op Number from SFDC.
Thanks & BR,
Tony Kim
Hi,
I have plan to connect our designed sensor and CY8CPROTO-062-4343W for Capsense evaluation.
Could you please share the sample project?
I'd like to get it as PSoC Creator's project if possible because I have experience with CapSense tuner and I don't need to do BT/WiFi evaluation.
Best regards,
Show LessHi,
I've looked on this site and tried some project code left with some of the discussions.
Forum Links I've tried:
PSoC6 RSSI value measurement issue
Is it possible to read RSSI value when core is in Deepsleep
I'm trying to read the RSSI values of received BLE messages with no real success.
Are there any working examples of accomplishing this goal?
I'm probably missing something simple.
Len
Show LessI am wanting to implement neuron network on PSOC 6. I see that Zerynth studio enables Python implementation on PSOC 6. Has anyone tried SensorFlow lite with this setup?
Thanks
Show LessIs it possible to get an interrupt when a BLE CRC check fails and if so, is it possible to stop a GATT write without response or GATT notification?
Show LessHello,
I'm trying to find an example on how to implement BLE with authentication based on FreeRTOS. Basically, I want my device to generate passkey, upon a connection request display it (e.g. output to UART) and then establish a connection. Are there any sample projects around?
The only I was able to find are not FreeRTOS-based and BLE interaction there is a bit different.
Also, where I could locate the full API documentation on BLE PDL? BLE_PDL_v2.10.pdf does not contain most of Cy_BLE_* API functions descriptions.
Thanks in advance,
Show LessI want to disable the DAP to prevent debug access from the SWD port and I am using this COM API to change lifecyle to secure. I am leaving all secureRestrict and deadRestrict settings as don't care from the example given in the API document. Is this the correct method? I cannot connect to the chip anymore with SWD after I run this. Do I need to set any bytes to 1 for the secureRestrict also?
byte[] secureRestrict = new byte[16];
byte[] deadRestrict = new byte[16];
bool voltageVerification = false;
byte lifecycle = 4; //secure
for (int i = 0; i < secureRestrict.Length; i++)
secureRestrict = 0xFF;
for (int i = 0; i < deadRestrict.Length; i++)
deadRestrict = 0xFF;
hr = pp.PSoC6_WriteProtection(lifecycle, secureRestrict, deadRestrict, voltageVerification, out strError);
Also, the COM API doesn't state how the 16 bytes map to the 2 bytes of SECURE_ACCESS_RESTRICT0 and SECURE_ACCESS_RESTRICT1. Is this how the mapping works?
[0] = bit 0, SECURE_ACCESS_RESTRICT0
...
[7] = bit 7, SECURE_ACCESS_RESTRICT0
[8] = bit 0, SECURE_ACCESS_RESTRICT1
...
[15] = bit 7, SECURE_ACCESS_RESTRICT1
Show LessWhen the PSoC6 is in the secure lifecycle, the SWD/JTAG port should be disabled. Is the check for disabling still done by software somewhere in the ROM code? The STM32 SWD protection can be bypassed by voltage glitching. Can this attack be done on PSoC6?
https://blog.kraken.com/post/3248/flaw-found-in-keepkey-crypto-hardware-wallet-part-2/
Show LessI'm using Creator 4.2 to make a test project for the CYBLE-416045-02, and the fitter is unable to place a digital output pin. The only thing unusual I did was turn on the output enable (the pin is the Tx for a multi-drop serial bus).
Here is the error I'm getting:
Error: fit.M0059: FFB and IO placement failed: Failed to find a valid placement for MODBUS_Tx(0). (App=cydsfit)
There are not too many pins assigned on this project:
Here's what the UART and pin look like:
I've attached the exported project. If anybody has any idea why this doesn't work, I'd sure appreciate knowing. Is there a way to get verbose output from the fitter, maybe?
Show Less