Is it possible to get an SAR ADC result's range detect status and sign into an 8-bit datapath with DMA? It seems that a 32-bit read would be right on the ADC's side, and now I'm trying to figure out how to get only two bytes of the result into the datapath. The range detect status is in byte 3 (bits 31:24) of the result, and the sign is available in byte 1 (15:8).

Could I use an xy loop to achieve this?

X loop 1: copy two bytes (bits 7:0 and 15:8) from result to D0. Increment source address by 1, but don't increment destination address. That copies byte 0 first, and then overwrites it with byte 1. So I'd end up with byte 1, which contains the sign, in D0.

X loop 2: copy two bytes (bits 23:16 and 31:24) from the result to D1 (same as above with different destination base address). The range detect bit would then be available in D1.

The Y loop destination increment would have to be &D1 - &D0.

Would it work that way or would the DMA transfer always drop the 24 MSBs of the ADC result? If so, is there an alternative way?

My current solution copies just the result into a 16-bit datapath that performs the range check and sign extraction, but that results in an overall hard-to-route solution resulting in undesired tradeoffs and setup time violations that I'd like to avoid by using an 8-bit dp only. Other alternatives would require an 8-bit dp to perform 16-bit operations, but those are different questions.

The BLE event handler that I set up with CyBLE_Start gets called with event = 0x00010005 twice after CY_BLE_EVT_GAP_ENCRYPT_CHANGE when accessing the device whether through the CySmart app or through other BLE clients. I can't seem to find what this 0x00010005 event is in the header file or documentation. Notably CY_BLE_EVT_MAX is 0xFFFF, and this event is greater than that max.

I collected a stack trace:

0 bleEventHandler(uint32 event = 65541, void * event_param = 0x80475cc) main_cm4.c 371 0x10080A9A (All)

1 Cy_BLE_GATTS_WriteEventHandler(cy_stc_ble_gatts_write_cmd_req_param_t * eventParam = 0x80475cc, cy_stc_ble_gatts_write_cmd_req_param_t * eventParam@entry = 0x80475cc) Generated_Source\PSoC6\pdl\middleware\ble\cy_ble_gatt.c 110 0x10083316 (All)

2 Cy_BLE_EventHandler(cy_en_ble_event_t event = <optimized out>, void * evParam = 0x80475cc) Generated_Source\PSoC6\pdl\middleware\ble\cy_ble_event_handler.c 772 0x10083B2C (All)

3 CyBle_GattCB() ?????? ?????? 0x1008CE14 (All)

4 att_notify_application() ?????? ?????? 0x10088296 (All)

5 se_req_handler() ?????? ?????? 0x10094B92 (All)

6 fsm_post_event() ?????? ?????? 0x1008ABC6 (All)

7 att_l2cap_data_cb() ?????? ?????? 0x1008817E (All)

8 l2cap_lp_data_read() ?????? ?????? 0x100937C4 (All)

9 hci_transport_read_data() ?????? ?????? 0x1008FF8C (All)

10 Cy_BLE_EventHandler(cy_en_ble_event_t event = <optimized out>, void * evParam = 0x8047760) Generated_Source\PSoC6\pdl\middleware\ble\cy_ble_event_handler.c 326 0x100836CC (All)

11 CyBleController_HciSoftSend() ?????? ?????? 0x100957F2 (All)

12 hci_td_deliver_acl_data_to_host() ?????? ?????? 0x100A646E (All)

13 llft_service_queue() ?????? ?????? 0x100A2E5E (All)

14 llf_task_start_routine() ?????? ?????? 0x100A2DB2 (All)

15 CyBle_StackTaskHandler() ?????? ?????? 0x10087024 (All)

16 OS_scheduler() ?????? ?????? 0x100A95F2 (All)

17 main() main_cm4.c 418 0x10080C2E (All)

My function is bleEventHandler at frame 0.

HI Cypress Team,

In my custom board which uses PSOC62 BGA part: CY8C624ABZI-S2D44, we are facing issue in configuring the pull-down.

Can you please let me know your feedback on below:

1) What is the Strong Pull down value for PSOC62?

2) What is the Weak pull down value for PSOC62?

3) I wanted to configure my IO (P12.0) as Input with Weak pull-down, Please let us know the proper procedure to configure it correctly.

4) The same design is working fine on PSOC4 based custom board.

In the attached project I'm getting warnings about asynchronous clock paths and setup time violations.

In general:

• how do I interpret the warnings, based on the timing report?
• are there any standard recipes to fix the underlying problems?

And specifically: how do I fix the timing issues in the attached project?

There are manly development kits and it is not easier to find out one that I require. My requirement is the kit including ARM Cortex-M4 MCU, 2 ADCs and 2 DACs. Which development kits are available?

Best Regards,

Adam

I am using PSoC 6 Kit CYBLE-416045-02 and CySmart BLE Dongle CY5677  (which is based on PSoC 4200).

I used the code example here for PSoC 6 as GATT OUT (Data Sender)

https://www.cypress.com/documentation/code-examples/ce222046-psoc-6-mcu-bluetooth-low-energy-ble-connectivity-ble-throug…

and used Project #24 for CY5677 as GATT IN (Data Reciever). I select the address of PSoC 6 from the list

PSoC-4-BLE/100_Projects_in_100_Days/Day024_Throughput at master · cypresssemiconductorco/PSoC-4-BLE · GitHub

The throughput is always 0 kpbs. What do I need to change for the GATT OUT on the PSoC 6 to make the data transfer work correctly?

Thank you

I'm familiar with PSoC 5LP, PSoC 4 and 6 products. I have a customer that needs a device with Bluetooth 4.0 (not BLE) support. What's the best PSoC and dev kit for this?

In the attached project I've set clk_peri to 72 MHz and my (UDB/datapath based) peripherals are clocked at 36 MHz (clk_udb), which is 72/2 MHz. I did this because 72 MHz or similarly high clock speed resulted in an error because clock_udb may not exceed clk_peri/2.

However, this error does NOT appear when I set clk_udb clock to 48 MHz, which is clearly faster than clk_peri/2. Why does this error message not appear then? It comes back when I increase from 48 to 56 MHz.