PSoC™ 6 Forum Discussions
hi.
I have a problem running the example code
When I run the code, I have a problem like the picture below.
I would like to know how to solve this problem.
thank you.
/*********************************/
development environment
- tool : PSoC creator 4.4, mobile CySmart app
- PDL Version : 3.1.4
- mcu : CY8C6347BZI-BLD43
/*********************************/
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I think the device with the most UDB's has the most resources for implementing verilog- would that be Psoc 5LP ? It seems Psoc 6 devices don't use much in the way of UDB's from what I see in one of the datasheets. Is that a correct assessment?
Show LessHello.
I am testing with CY8CKIT-062-WIFI-BT.
Threre is an emWIN_TFT_FreeRTOS example, but the bitmap image is displayed slowly.
I'm not sure if it's the effect of RTOS, but is there an example that the bitmap image is output quickly?
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Hi,
In one of my CY8CPROTO-062-4343W boards I had to break apart the KitProg3 in order to program a custom board I had built. That worked fine. I made a jumper cable to keep programing the mutilated board, but now KitProg3 aborts with the errors:
TARGET: psoc6.cpu.cm0 - Not halted
in procedure 'program'
Polling target psoc6.cpu.cm0 failed, trying to reexamine
Examination failed, GDB will be halted. Polling again in 100ms
** Program operation failed **
The board is powered with 5V applied to the 5V regulator, and is still alive, blinking with the last project programmed with the KitProg3 still attached. I don't see in the schematics any other connection needed to program it. What could be wrong?
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Hello,
I am using CYBLE-416045-02 modul which sends and receives some values over BLE from App and in particular I started from example project CE220960 – PSoC 6 MCU BLE Upgradable Stack DFU.
In my project I added a simple library to read some values from a GPS and send these values over BLE to App.
I keep getting an error message during generation of the bootloadable file (.cyacd2):
ERROR: E:\CE220960\DFU_BLE_Upgradable_Stack_App2.cydsn\CortexM4\ARM_GCC_541\Release\DFU_BLE_Upgradable_Stack_App2_link.elf section `.text' will not fit in region `flash_app2_core1'
ERROR: section .cy_app_signature loaded at [1004effc,1004efff] overlaps section .text loaded at [10045000,1004fa9b]
ERROR: region `flash_app2_core1' overflowed by 0 bytes
How I can fix this?
What am I doing wrong?
Thanks in advance for any replies.
Lucia
Show LessHi,
If I have understood it correctly the boot process is as follows:
- The processor starts from the internal ROM circuit that controls the integrity of the BOOT Flash section in flash memory with a 128-bit truncated SHA256 digest before jumping to flash.
- The BOOT Flash is executed which checks the signature of the application before jumping to it.
- The application runs (on the Cortex M4 core)
The questions I now have is:
1.1 I have found information that the fuse bits in the eFuse OTP area can be programmed from ‘0’ to ‘1’ (which blows the fuse) but not the other way around.
If I have understood it correctly, the ‘0’ valued bits of the SECURE_HASH can still be programmed to ‘1’ and that is why the SECURE_HASH_ZEROES area exists to check if there is still the same number of zeroes as when programmed.
Is this correct? If so can the ‘0’ value bits of the SECURE_HASH_ZEROES also be changed?
2.1 Can a user defined bootloader be programmed to the BOOT flash sector, i.e can a custom 2nd stage bootloader be used?
Best regards,
Michael
Show LessI'm using a CY8C6137 PSoC 6 connected via I2C to a device using clock stretching. The PSoC 6 is the master and the device the slave. Clock stretching is done between the data and the acknowledge.
When the device transmits it holds the SCL line low after the 8th bit while it prepares the next byte, releases the SCL line and then reads the ACK bit from the PSoC 6. When the device receives, it holds the SCL line low after it receives the 8th bit then sends ACK or NACK.
How is I2C clock stretching handled in the PSoC 6? It's no problem if basic APIs need to be modified as I already have done so for other purposes.
Show LessHi,
A few weeks ago I reported a similar problem in my application with TCPWM Timers. Unfortunately, in that opportunity we couldn't reproduce the problem using a simplified Hello World example. Now I have the same problem with TCPWM in PWM mode. Like before, the only sure way to change its period is by deinint the PWM and reinit it with the new period.
But this time I could reproduce the problem in the Hello World example, which I uploaded here. For what I could pick up from the PDL documentation and other comments this should be the correct way to change the PWM period, but it does nothing:
/* validate frequency ranges */
if (_timer_frequency < MIN_FREQUENCY || _timer_frequency > MAX_FREQUENCY)
return;
Cy_TCPWM_TriggerStopOrKill(PWM_1_HW, PWM_1_NUM);
Cy_TCPWM_PWM_SetCounter(PWM_1_HW, PWM_1_MASK, 0);
uint32_t new_period = _timer_clock / _timer_frequency;
Cy_TCPWM_PWM_SetPeriod0(PWM_1_HW, PWM_1_MASK, new_period);
Cy_TCPWM_PWM_SetPeriod1(PWM_1_HW, PWM_1_MASK, new_period); // just in case!
Cy_TCPWM_TriggerReloadOrIndex_Single(PWM_1_HW, PWM_1_NUM);
the clock frequency is 10 KHz and the PWM range needed is 1 to 400 Hz. Nothing spectacular.
uncommenting //#define USE_REINIT_MODE at line 200 of main.c you can select the code above or the full reinit mode which actually works.
I left there the older Timer test routines, but the timer init is commented out in main(). The loop reads the debug terminal awaiting single key commands. P should change the PWM from 1 to 10 Hz that toggles the LED accordingly.
The PDL documentation should have complete examples of these functions A to Z. Not just a snippet with a line of comment.
Show LessI wonder if is it possible to access the QSPI Flash from M0+.
The example provided in the modus toolbox seems to use the M4 ( as there is the HAL lib that is not usable with M0 ).
Please help
Thanks
S
Show LessWhen I create a task, it seems to run just fine. But as soon as I call any blocking function (vTaskDelay), the app never seems to re-enter the Ready state. I have configTICK_RATE_HZ is defined in FreeRTOSConfig.h. Is there anything else I can look at?
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