PSoC™ 6 Forum Discussions
Hello!
Can someone guide me with IrDA RX pin configuration.
Actually my IrDA reception interrupt is not working. I am running my UART with DMA. It is running fine in standard mode. But when I put it in IrDA mode the reception interrupt is disabled.
Please share your suggestions. Any kind of help would be highly appreciated.
Thanks.
Show LessHello Team Cypress,
Do you have any reference design guide using PSoC 6, 63 with BLE series (CY8C5347) for Smart health tracking device?
One of my client is developing Smart ring for fitness and health, and is considering to use CY8C5347.
The client have checked Maxim's guide on such Health device reference design,
(Wearable & Portable Monitoring IC Applica | Maxim Integrated)
and wants to see if Cypress carries similar health care application guide or reference board to check .
Side note:
Desired design features on Smart ring for fitness and health :
-Heart rate
-Blood oxygen data
-Wireless charging
If you can share any design information available for PSoC6 63 or recommend any other Cypress products with such device reference design note, that would be really helpful to recommend Cypress products further.
Thank you for your help and considerations.
Sincerely,
Ben
Hello, I have designed in CY8C6316BZI-BLF53 into a medical product that is going to be used for a clinical trial. I have a handful of boards through our testing have broken and they have done so in the same way. The PSOC is getting power on VDDD and VDDA, but the internal buck isnt working. The latest PCBA that did this had been running a treatment for 40minutes and then it just died in the manner previously described. I couldnt find any schematic on how the power rails are laid out internal to the PSOC and what could have broken exactly in the PSOC for the buck to not work. On these non working PCBAs I am supplying VDDD and VDDA with 3V from a bench supply. Vbuck measures 2.5V, VDDR_HVL measures 1.5V, VDD_NS measures 3V. All the other rails are 0V. Vind1 and Vind2 are both at 0V. The 32.768kHz crystal is running. Is there any information you can supply to help prevent this from happening or any internal PSOC buck schematic? We are in development and dont want this to become a big issue down the road.
I have noticed that in the literature there is a decoupling cap on Vind2 which is missing in my schematic, but unsure without more information if that is the cause of the issue.
Slainte!
Jeff
Dear all,
I am getting started with CY8CPROTO-062-4343W and Modus Toolbox to build a RAM/ROM emulator, connected to the address and data busses of a 8-bit computer. As such, I want to decode some address lines and some other control signals to generate an interrupt (chip select), so the PSoC can either read the 8bit data input and store internally, or output a 8-bit pattern for the provided address.
The operation needed are only combinatorial and the LUTs could certainly do that. But here is my - stupid - problem : how can I configure the LUT ouput to go to one PSoC port and trigger an interrupt ? HSIOM is supposed to allow this routing, but I could not understand how to configure this in Modus Toolbox. Also, can I still read from the firmware the GPIO inputs for signals that are routed to the LUTs (as I will need to read the address lines that were used to define the chip select/interrupt signal) ?
Thanks in advance for your help, my apologies for the rookie's questions !
Philippe
Show LessHi,
I am trying to use the CYPRESS PSoc6 CY8CKIT-BLE and get data from the ADC. I am trying to store the data in each loop in a sort of array and save data for every 150 loops and save it together in the SRAM. I am not sure which functions and libraries will work best for me in this situation.
Could someone help me on the same?
Thank you for your help.
Show LessHi All,
Probably many people struggle finding good quality PCB manufacturer for small pitch Cypress BGA chips.
If you have any recommended PCB maker would be great to know.
I have PCB with CY8C6347FMI chip that consist via-in-pad and micro vias for that chip.
Here is most critical parameters
Min track/spacing 3.3 mil
Min annual ring size 0.05 mm
Min BGA pad size 0.27mm
BGA pad clearance 3.2 mil
Min Hole Diameter 0.15 mm
Thanks in advance.
Show Less
Hi,
Is there a possibility to have two or more memory slots in XIP mode without switching between them manualy?
Now it is only possible to manually select QSPI slave, for example using this sequence:
cyhal_qspi_init(&qspi_psram_obj, QSPI_IO0, QSPI_IO1, QSPI_IO2, QSPI_IO3, NC, NC,NC, NC, QSPI_CLK, PSRAM_SSEL, QSPI_FREQ, 0);
cyhal_qspi_slave_select_config(&qspi_psram_obj, FLASH_SSEL);
/*Entering XIP mode and working with external PSRAM on slot 0...*/
cyhal_qspi_select_active_ssel(&qspi_psram_obj, FLASH_SSEL);
/*Entering XIP mode and working with external FLASH on slot 1...*/
Regards,
Gintaras
Show LessHello
I have used PSOC 4 and 5 since long and I remember that Ports 0,1,2 and 3 are connected to HSIOM in PSOC 4. Therefore UDB output can be routed through only these ports.
I am using PSOC 61xx MCU and there are 13 ports, I would like to know which ports support UDB connections out of the 13 ports and where can I find more information on this.
Also, there are two smart IO ports that support Boolean operations. Does this consume the UDB resource?
Thank you
Show LessI upgraded my firmware to KitProg3 and wanted to run one of the example codes.
The device will not even get acquired. How doI fix this issue?
Open On-Chip Debugger 0.10.0+dev-4.2.0.1430 (2021-03-05-08:22)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
adapter speed: 2000 kHz
adapter srst delay: 25
adapter srst pulse_width: 25
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
cortex_m reset_config sysresetreq
cortex_m reset_config sysresetreq
Info : Using CMSIS loader 'CY8C6xxx_SMIF' for bank 'psoc6_smif0_cm0' (footprint 11100 bytes)
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.21.1005
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 3.278 V
Info : kitprog3: acquiring the device (mode: reset)...
Error: kitprog3: failed to acquire the device
Info : clock speed 2000 kHz
Error: DAP 'psoc6.cpu' initialization failed (check connection, power, transport, DAP is enabled etc.)
** OpenOCD init failed **
shutdown command invoked
** Program operation failed **
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Error executing event reset-deassert-post on target psoc6.cpu.cm0:
C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg:108: Error:
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 279
in procedure 'mxs40_reset_deassert_post' called at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/psoc6_common.cfg", line 131
at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg", line 108
Error executing event reset-deassert-post on target psoc6.cpu.cm4:
C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg:108: Error:
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 279
in procedure 'mxs40_reset_deassert_post' called at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/psoc6_common.cfg", line 166
at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg", line 108
Info : psoc6.dap: powering down debug domain...
Warn : Failed to power down Debug Domains