PSoC™ 6 Forum Discussions

What is the correct minimum endurance for embedded flash in a PSoC 6?

Datasheets for PSoC 6 claim 100k cycles minimum for Flash Endurance.

TRMs claim endurance of 10k cycles.

Reference section 6.5 Memory in PSoC 62x7 datasheet. Reference Section 13.1.1 Features in PSoC 6 MCU: CY8C62x6, CY8C62x7 Architecture TRM, Document No. 002-20730 Rev. *J (page 146):

Search for "endurance" to find the stated spec in other PSoC 6 datasheets and TRMs.

Greg

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Our company has a device that uses two microprocessors; the CY8C4245PVI-482 and the CYBLE-416045-02 (PSoC 4 and PSoC6).  The device will be in a case that cannot be reopened, but it needs to be reprogrammable for updates, especially during the beta testing phase, but also in mass production so customers can add features and update software.

Our hardware/software developer is running into difficulty creating a bootloader that will make the two chips reprogrammable through the USB-C port.  They cite the lack of support from infineon for chips like these that came from Cypress.  

Their solution was to offer reprogrammability through Bluetooth on the PSoC 6 using a smartphone app, but now they are saying it is too difficult and will take up too much space on the processor.

Is this capability within reach using either USB or Bluetooth?  Does anyone have tips on how I can get some support for our developers?

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Dear Sir or Madam,

I have some underlying logic questions I'd like to ask about Capsense.

1. I don't have ADC set in the setup, but Capsense is still running successfully. Does Capsense use an ADC? If so what is the frequency of that ADC? Or was some other method of signal conversion used?

2. What is the sample output rate of Capsense? What is the data format? I need to synchronize the Capsense signal with other signals, so I need to know about it. 

3. Is the scan time here equivalent to the Capsense conversion rate?

Best regards

 

 

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Hi, I'm using CY8CKIT-062-WIFI-BT EVK.

I'm creating a PWM waveform with P0.3 using TCPWM[0].CNT[1].

Is there a way to use another Timer (e.g. TCPWM[0].CNT[0]) to generate an interrupt when TCPWM[0].CNT[1] outputs 100 times (100 PWM cycles)?

In other words, when TCWMP[0].CNT[1] outputs 100 times, can the interrupt of TCPWM[0].CNT[0] occur once?

Thanks and Regards,

YS

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Hi, my name is Harith, I am a student from Malaysia. I am really new to Infineon Xensiv Board, and currently I am using KIT CSK BGT60TR13C. Before this I am using Arduino. So here I have some questions about this kit.

1. What is the best language that is suitable and easy for developing a project with the Kit

2. Does Python language support the Kit? If it is supported, is it easier for me to use Python?

3. What IDE I can use other than Eclipse IDE?

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¡Hola comunidad! les comento que estoy realizando un proyecto en la cual quiero implementar una pantalla LCD genérico 16x2 mediante I2C. Estuve investigando algunos drivers para poder manejar dicha pantalla mediante Eclipse IDE modustoolbox y utilizarlo en mi placa CY8CPROTO-062-4343W PSoC6, pero no estoy encontrando buenos resultados, solamente ejemplos implementados a PSoC5LP. ¿Me podrían brindar información de como puedo manejar este pantalla LCD o que me recomiendan hacer? ¡muchas gracias! Show Less

Originally very normal, suddenly unable to download the code, the following is the console display info？

 

Started by GNU MCU Eclipse
Open On-Chip Debugger 0.10.0+dev-4.1.0.1058 (2020-08-11-03:47)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
adapter speed: 2000 kHz
adapter srst delay: 25
adapter srst pulse_width: 25
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
cortex_m reset_config sysresetreq
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.21.1005
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 3.328 V
Info : kitprog3: acquiring the device...
Error: kitprog3: failed to acquire the device
Info : clock speed 2000 kHz
Error: DAP 'psoc6.cpu' initialization failed (check connection, power, etc.)
Info : psoc6.dap: powering down debug domain...
Warn : Failed to power down Debug Domains

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How do the two separate MCU cores in a PSoC 6 access their instructions independently?

Is there a block diagram of the dual core PSoC 6 instruction memory architecture that would aid an explanation?

Under what conditions will an instruction fetch from one MCU, cause the other MCU to wait?

Greg

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