PSoC™ 6 Forum Discussions
We are using the CY8CMOD-064S0S2-4343W board design developed by Cypress and have created an identical board called Cloud Lock.
On the new Cloud Lock board the VCCD input supply is designed to use the internal Buck regulator as the source, same as the original design.
VDD_NS is sourced off board using a 2.5vdc supply and is the source for the internal buck regulator.
The output of the internal buck regulator is VIND1 this goes through a 2.2uH inductor to VBUCK which supplies the input power to VCCD through a zero ohm resistor (R26 see attached PDF for schematic)
When the power is first applied to the board there is no output from the internal buck on VIND1 and in looking at the TRM for the P64 the buck defaults to an “OFF” state.
The first-time power is applied to the P64 how do we get the buck regulator to output so we can get the device operational?
Show LessHi Everyone,
A few weeks ago I posted a message here complaining that Cy_TCPM_Counter_SetPeriod() is not behaving as documented. In my application I need to dynamically change the period of a counter anywhere from 1 to 400 Hz to generate a periodic interrupt that will trigger other events. The problem was that no mater what period I tried to set, the counter ignored it and remained running at the initial frequency when it was initialized. Frustrated I resorted to just de-initialize and reinitialize the counter with the new frequency. A few weeks later the problem came back to bite me again when I needed to change the period of a timer in PMW mode, and posted a second message here.
After detailed code review and debugging, and stepping through the code, I finally found a few errors in my code, AND, understood how the API really has to be used. This is not clearly documented anywhere, at least in the places where I looked (this forum and others).
First, don't repeat my errors:
1. Pay attention to the type of parameters that each function expects. For example,
Cy_TCPWM_TriggerStart_Single(Timer_1_HW, Timer_1_NUM); // The second parameter must be the timer NUMBER
Cy_TCPWM_TriggerStart(Timer_1_HW, Timer_1_MASK); // The second parameter must be the timer MASK (or the OR '|' combined mask of several timers, if you want to start them all in sync)
2. Double check the parameters used in the PDL documentation. In one instance the example has the second parameter incorrect (it uses counter MASK where it should use counter NUMBER, twice!). All xx_Single() versions of the functions work on a single timer and expect the timer number. That error in the example led me to believe that xx_MASK and xx_NUMBER are interchangeable, when they are NOT.
3. You must STOP the counter to make changes to the period, duty cycle, compare values, etc. There may be instances where this is not necessary, but better safe than sorry, in the PDL documentation the examples do not mention this, (at least for the functions that I used).
4. It seems that Cy_TCPWM_TriggerStopOrKill_Single() is not an atomic operation. You must test and make sure that the counter has stopped before continuing. This was the principal problem I had since the beginning.
So, here is the the safe method to alter counter parameters that I came up with:
uint32_t loops; // this variable is for debugging purposes only
void Change_Timer_1_Frequency(uint32_t _new_frequency)
{
uint32_t period = 0;
/* validate frequency range */
if (_new_frequency < MIN_FREQUENCY || _new_frequency > MAX_FREQUENCY)
return;
period = _Timer_1_clock / _new_frequency;
loops = 0;
Cy_TCPWM_TriggerStopOrKill_Single(Timer_1_HW, Timer_1_NUM);
/* IMPORTANT: wait for the timer to stop before changing registers */
while (Cy_TCPWM_Counter_GetStatus(Timer_1_HW, Timer_1_NUM) & CY_TCPWM_COUNTER_STATUS_COUNTER_RUNNING )
loops++;
Cy_TCPWM_Counter_SetCounter(Timer_1_HW, Timer_1_NUM, 0);
Cy_TCPWM_Counter_SetPeriod(Timer_1_HW, Timer_1_NUM, period);
Cy_TCPWM_TriggerStart_Single(Timer_1_HW, Timer_1_NUM);
}
I introduced the variable Loops for testing purposes. In a simple, Hello World type of program when only this code is running Loops may be 0, most of the time. But as the program grows in complexity with interrupts and external events going on at the same time, that won't be the case. In my application Loops ends up anywhere from 65 a to over 600 iterations before the counter stopped!
In summary, I thing that PDL is a good helper, but its documentation is minimal and the examples just snippets not really tested in an actual program. As a former boss of mine used to say "Trust is good, check is better!"
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In the description of cyhal_i2c_master_write():
"I2C master blocking write.
This will write size
bytes of data from the buffer pointed to by data
. It will not return until either all of the data has been written, or the timeout has elapsed"
Will this function also block the interrupts (e.g. uart, timer ) until it finished?
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Hey Sir,
MCU CY8C6347BZI-BLD54 is used as a CPU on our product and it has been produced for 50K-100K units. However, there are a few units (less than 1%) having boot-up issue after executing the process of secure boot. The failure symptoms are listed below:
1. Power up for several cycles and then finally it could boot up successfully. The cycle time of powering up can't be calculated. It's a random.
2. Always fail to boot up so it becomes a brick.
3. 1 unit succeeds to boot up intermittently.
The eFuse of these units is burned successfully if we check the eFuse bit after the unit succeed to boot up. Thus, we can't read any debug information from the SWD port. Then some signal waveforms are captured and compared on both the situation of successful and fail boot-up. The main differences are
1. The power rail behavior of MCU_VIND2, MCU_VRF, and MCU_VBUCK1
2. The activated timing of SWDIO
Please refer to the attachment for more detail waveforms. We suspect this issue results from the process of eFuse burning but we don't have solid evidence to prove it. Thus, we need your thoughts and insights on this issue. It's getting more critical now due to the increasing production volume. Thanks.
Show LessI pre-ordered this CY8CKIT-062-BLE dev board from Digi-Key and it was shipped 28-SEP-2017 Inv # 59555866.
It won't program. I've tried the on-board Kitprog and a Miniprog. I've updated the KitProg using PSOC Programmer. I've tried updating via fw-loader. Nothing works. From within PSOC Creator 4.4, Kitprog says it programmed. The miniprog won't program from within PSOC Creator 4.4.
I looked at the silicon and it says "ES" as in "Engineering Sample" CY8C6347BZI-BLD53ES1725 62 5565. The board sticker says "121-60367-01 Rev 08" and "1732SO00102". I read online there were issues with the early versions of this board and to contact support. I sent a message via the Infineon website but I'm not sure that it went to the right place.
Is there something I can do to make this board usable? I know it's been a long time... I just recently got back into working with motor controls and I need the features present in the PSOC 6.
Show LessI don't know how to connect the VREF pin(49pin).
Should I connect a capacitor?
If so, how much capacity should I connect?
I am trying to get CE220960 working for PDL 3.1.5 to I can incorporate BLE DFU in my project which uses PDL 3.1.5. I was able to get the project to build (see my previous post ), but now I am having an issue updating the stack application (App1) using. I am using PSoC Creator 4.4, PDL 3.1.5, DFU_BLE_Upgradable_Stack_Apps, CySmart 1.3, and CY8CKIT-062-BLE hardware.
Using CySmart, I am able to do the "Application only update" which is App 2, but I there is an error when executing the Application and stack update. I get the following error:
Not sure how this could be happening because the DFU update is the same application that's already on the device, so it should just fit right in where the other instalment was. I tried increasing the size of each flash region with no luck. Any idea what could be going wrong here?
Show LessHi
The PSoC-6 PDL lists some Clock functions, but when I use them in PSoC Creator, they are not identified or declared.
these include:
Cy_SysClk_ClkPathGetFrequency() and Cy_SysClk_ClkHfGetFrequency()
I am using PDL 3.1.5
Do I have to include certain headers or libraries to the project ?
thanks
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