PSoC™ 6 Forum Discussions

Hello,

I have installed the latest ModusToolbox and am trying to develop on the PSoC 62S2 Wi-Fi BT Pioneer Kit. 

Unfortunately, I receive the following error when trying to program or debug the board using Modus Toolbox IDE:

* The detected device does not match the configuration file in use.
* Flash programming will not work. Please use the "psoc6_2m.cfg"
* configuration file, or attach a kit that matches the configuration file.

I have checked and psoc6_2m.cfg is in use. The real issue seems to be that only the Cortex-M0 core is detected during programming. See below the complete debug log: psoc6.cpu.cm0 is found, but cm4 is not. Bizarre.

Additionally, there is another worrying line because I am using Apple M1 based MacBook Pro and not x86 Intel MacBook. 

Launching GDB: /Applications/ModusToolbox/tools_2.4/gcc/bin/arm-none-eabi-gdb

This GDB was configured as \"--host=x86_64-apple-darwin10 --target=arm-none-eabi\

Complete log from the debug terminal below:

Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.30.1155
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 3.288 V
Info : kitprog3: acquiring the device (mode: reset)...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x6ba02477
Info : psoc6.cpu.cm0: hardware has 4 breakpoints, 2 watchpoints
***************************************
** Silicon: 0xE453, Family: 0x102, Rev.: 0x12 (A1)
** Detected Device: CY8C624ABZI-S2D44
** Detected Main Flash size, kb: 2048
** Flash Boot version: 3.1.0.378
** Chip Protection: UNKNOWN
Started by GNU MCU Eclipse
*******************************************************************************
***************************************
terminate command invoked
* The detected device does not match the configuration file in use.
* Flash programming will not work. Please use the "psoc6_2m.cfg"
* configuration file, or attach a kit that matches the configuration file.
*******************************************************************************
Info : psoc6.dap: powering down debug domain...

Looking for ideas how to fix this bizarre issue and program/debug the board.

Thanks,

Dimi

Hi,

I am using Modus Toolbox v2.4, the latest cysecuretools, the latest KP3 firmware, and my Kit is CY8CKIT-064S0S2-4343W.

I get the error stated in the subject when trying to program the default amazon freertos project available at https://github.com/aws/amazon-freertos 

I am asking for your advice and guess what might be the issue. 

Open On-Chip Debugger 0.11.0+dev-4.3.0.1746 (2021-09-16-07:59)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
** Main Flash size limited to 0x1D0000 bytes
adapter speed: 2000 kHz
adapter srst delay: 0
adapter srst pulse_width: 5
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
** Using POWERUP_DELAY: 5000 ms
** Using TARGET_AP: cm0_ap
** Using ACQUIRE_TIMEOUT: 15000 ms
Info : Using CMSIS-flash algorithms 'CY8C6xxA_SMIF_S25FL512S' for bank 'psoc64_smif_cm0' (footprint 11500 bytes)
Info : CMSIS-flash: ELF path: ../flm/cypress/cat1a/CY8C6xxA_SMIF_S25FL512S.FLM
Info : CMSIS-flash: Address range: 0x18000000-0x1BFFFFFF
Info : CMSIS-flash: Program page size: 0x00001000 bytes
Info : CMSIS-flash: Erase sector size: 0x00040000 bytes, unified
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Using CMSIS-DAPv2 interface with VID:PID=0x04b4:0xf155, serial=040F135101220400
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.30.1155
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 3.324 V
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x6ba02477
***************************************
** Use overriden Main Flash size, kb: 1856
** Silicon: 0xE4A0, Family: 0x102, Rev.: 0x12 (A1)
** Detected Device: CYS0644ABZI-S2D44
** Flash Boot version: 4.0.2.1842
** SFlash version: 310192
***************************************
Info : gdb port disabled
Info : starting gdb server for psoc64.cpu.cm0 on 3333
Info : Listening on port 3333 for gdb connections
Info : Deferring arp_examine of psoc64.cpu.cm0
Info : Use arp_examine command to examine it manually!
Error: Target not examined, will not halt after reset!
Info : SWD DPIDR 0x6ba02477
Info : Waiting up to 15.0 sec for the bootloader to open AP #1...
Error: AP #1 is still not opened: Failed to access debug sybsystem, giving up
Error executing event reset-deassert-post on target psoc64.cpu.cm0:
embedded:startup.tcl:788: Error:
in procedure 'program'
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 788
TARGET: psoc64.cpu.cm0 - Not halted
in procedure 'program'
Info : SWD DPIDR 0x6ba02477
Polling target psoc64.cpu.cm0 failed, trying to reexamine
Info : SWD DPIDR 0x6ba02477
Info : SWD DPIDR 0x6ba02477
Error: Failed to read memory at 0xe000ed00
Examination failed, GDB will be halted. Polling again in 100ms
** CM0 Program operation failed **
Polling target psoc64.cpu.cm0 failed, trying to reexamine
Info : SWD DPIDR 0x6ba02477
Info : SWD DPIDR 0x6ba02477
Error: Failed to read memory at 0xe000ed00
Examination failed, GDB will be halted. Polling again in 300ms
Info : Deferring arp_examine of psoc64.cpu.cm0
Info : Use arp_examine command to examine it manually!
Error: Target not examined, will not halt after reset!
Info : SWD DPIDR 0x6ba02477
Info : Waiting up to 15.0 sec for the bootloader to open AP #1...
Error: AP #1 is still not opened: Failed to access debug sybsystem, giving up
Error executing event reset-deassert-post on target psoc64.cpu.cm0:
embedded:startup.tcl:1075: Error:
in procedure 'program'
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 788
in procedure 'program'
in procedure 'program_error' called at file "embedded:startup.tcl", line 1112
at file "embedded:startup.tcl", line 1075
TARGET: psoc64.cpu.cm0 - Not halted
in procedure 'program'
** CM4 Program operation failed **
Info : SWD DPIDR 0x6ba02477
Info : Deferring arp_examine of psoc64.cpu.cm0
Info : Use arp_examine command to examine it manually!
Info : SWD DPIDR 0x6ba02477
Info : Waiting up to 15.0 sec for the bootloader to open AP #1...
Error: AP #1 is still not opened: Failed to access debug sybsystem, giving up
Error executing event reset-deassert-post on target psoc64.cpu.cm0:
embedded:startup.tcl:1075: Error:
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 788
in procedure 'program'
in procedure 'program_error' called at file "embedded:startup.tcl", line 1112
at file "embedded:startup.tcl", line 1075
Polling target psoc64.cpu.cm0 failed, trying to reexamine
Info : SWD DPIDR 0x6ba02477
Info : SWD DPIDR 0x6ba02477
EError: Failed to read memory at 0xe000ed00
xamination failed, GDB will be halted. Polling again in 700ms
Info : psoc64.dap: powering down debug domain...

l have successfully program the board but my screem is always blank.

Hello,

I am developing an audio processing application using the CY8KIT-062-Wifi-BT board.  I started from the PDM to I2S example and I changed the code in order to do bypass/processing live, instead of storing the audio in a big buffer and then play it. This works fine.

My next step is to implement an audio jack microphone instead of the PDM one. I removed all the PDM-PCM code and implemented the I2S RX. I configured the codec to enable the ADC, mic power and mic gain, according to the board characteristics. I am using a 3-channel AHJ headset with microphone that was tested in other devices.I also implemented the RX callback same way I did with the TX, but the callback is never called. I checked both RX clocks (WS and BCKO) and they look fine. Same with the RX_SDI pin, the adc output signal appears correctly in the oscilloscope. I suppose there is something wrong with the gain of the microphone or the audio format, but I don't know. TX works fine the same way.

I attatch my main code. Any help would be appreciated. 

Thanks,

jp

Hi.

I saw an article about collaborating with Picovoice.

https://www.infineon.com/cms/en/about-infineon/press/market-news/2021/INFCSS202110-007.html

Can this program the Picovoice sample code on the PSoC 6 evaluation board?
If so, where can I get the sample code?

If you want to evaluate in a different way, could you tell me how?

Best Regards.

I trying to make OSB (on screen display) for analog video (NTSC format) with 640X480 pixels resolution.
To synchronize to the external video i using external board to catch the sync pulses from analog video, every sync type connected to GPIO and to ISR.
The horizontal sync pulse is active once a 64uSec, so once 64uSec trigger the DMA programmatically and send the data to Control register which connected GPIO
(the GPIO connected to the video line via diode).
The GPIO rise the voltage (distortion) at specific point of time and it make the pixel white. With this method i can draw on the analog video.

At LP5 (CY8C5888LTI-LP097) -----
This method work and stable, but i facing two main problems:
1)At max clock (PLL at 80Mhz) i can reach max 464 pixels per line (for each 52uSec of visible line 464 distortions on the video line) - need to have 640 distortions for 52uSec piece of time.
2)I can't reach 640X480 buffer size (640X480 /1024 =300KB ) - i use Byte per pixel (CY8C5888LTI-LP097 is max 64KB SRAM).

At Posc 6 (CY8C6347BZI-BLD53) -----
To overcome LP5 problems i try to use Posc 6 (CY8C6347BZI-BLD53) but i stuck with the DAM configurations, i see on the oscilloscope the Bytes i try to send, but
the rate is very slaw (8 Bytes per 500uSec), according to the datasheet the DMA use Clk_Slow , but i configured it to 100Mhz.

1-What could be the problem with the configuration?
2-It seems that the Bytes are not stable at this slow rate (although using an old oscilloscope..)
3-At lp5 the DMA cannot access to all the SRAM, is it the same with PSOC6?
4-Is there any way to send bit by bit instead of byte?

I'm try to set up the ADC using the device configurator, as follow:

- Vref = Internal Reference (from AREF Resource)   1.2V

- No. of channel =2

-Ch0 Vplus= P10.0,  Cho Vminus=AREF vref

-Ch1 Vplus= P10.1,  Cho Vminus=AREF vref

After I set this the Notice list Show:    "Task: ADC clock frequency, 2000000, is out of the supported range (1.7 to 1.8 MHz). [CY8C6244LQI-S4D92: 12-bit SAR ADC 0 [clk_freq_display]]"

Then I try to set the "Clock Select" from "Deep Sleep Clock" to  "Peripheral Clock Divider" ,  and "Clock" as "8 bit Divider 2  clk"   ,  the Clock frequency shows as 1.786MHz  +/- 2.4%.

But the notice list shows Task:      "Resource 'amuxbus_a_sar' is overused between nets 'csd[0].csd[0]:sense:3, pass[0].saradc[0].sar[0]:Vminus:0, pass[0].saradc[0].sar[0]:Vminus:1' [CY8C6244LQI-S4D92: Routing Results]"

How can I solve this?