PSoC™ 6 Forum Discussions

Dears,

I would like to test FPU in PSOC6 in modus toolbox 2.4 environment

I installed CMSIS DSP and set all variables in makefile (DEFINES, INCLUDES, LDLIBS as noted in another posts like https://community.infineon.com/t5/PSoC-6/How-to-use-ARM-CMSIS-DSP-lib-in-ModusToolbox2-4/m-p/342494 ...) when VFP_SELECT=hardfp all source codes compiles ok and project seems to run normally but I still think that FPU is not used... So I would like also test with "software emulated" and compare execution time.

But when I set makefile variable VFP_SELECT=softfp or to empty value (as default) But now I got compilation errors like this "ld.exe: failed to merge target specific data of file...":

Linking output file mtb-example-psoc6-lptimer.elf
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_sin_f32.o) uses VFP register arguments, C:/Users/xxxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_sin_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_cos_f32.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_cos_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_mult_f32.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_mult_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_add_f32.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_add_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_common_tables.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_common_tables.o)
collect2.exe: error: ld returned 1 exit status
make[1]: *** [../mtb_shared/core-make/release-v1.9.1/make/core/build.mk:529: C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf] Error 1
make: *** [../mtb_shared/core-make/release-v1.9.1/make/core/main.mk:434: secondstage_build] Error 2
"C:/Users/xxx/ModusToolbox/tools_2.4/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_MAKE_IDE_VERSION=2.4 CY_IDE_TOOLS_DIR=C:/Users/xxx/ModusToolbox/tools_2.4 -j12 all" terminated with exit code 2. Build might be incomplete.

What is going bed ? 

Best Regards

Radim

Hi All,

In the case of the CYB06445LQI-S3D42 product, is there any data that shows how many ms it takes to 'Secure Boot'

from the device reset to the user application starts?

Even rough information is fine.

Best regards,

Alex Park.

Dear Receiver, 

I'm learning PSoC 6 recently.

I would like to know the relationship PDL and Device Configurator. (Please refer to the attached file,,,)

I feel PDL is Device Configurator. Is this correct ?! 

If not, where to check the PDL version in MTB ?!

Besides, what's the relationship between PDL and Device Configurator ?!

Thank you so much.

Hello, I have a question about the problem that occurred while creating the file 'bin' in 'Keil'.

; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
    ER_FLASH_VECTORS +0
    {
        * (RESET, +FIRST)
    }

    ER_FLASH_CODE +0 FIXED
    {
        * (InRoot$$Sections)
        * (+RO)
    }

    ER_RAM_VECTORS RAM_START UNINIT
    {
        * (RESET_RAM, +FIRST)
    }

    RW_RAM_DATA +0
    {
        * (.cy_ramfunc)
        * (+RW, +ZI)
    }

    ; Place variables in the section that should not be initialized during the
    ; device startup.
    RW_IRAM1 +0 UNINIT
    {
        * (.noinit)
    }

    ; Application heap area (HEAP)
    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
    { 
    }

    ; Stack region growing down
    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
    {
    }

    ; Used for the digital signature of the secure application and the
    ; Bootloader SDK application. The size of the section depends on the required
    ; data size.
    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
    {
        * (.cy_app_signature)
    }
}

; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
    .cy_em_eeprom +0
    {
        * (.cy_em_eeprom)
    }
}

Above is the contents of the 'sct' file in the ToolChain_ARM folder.

If you proceed with the build in the current situation, it will be displayed as a folder, not a file, as shown below.

If i use 'hex2bin' to switch to 'bin', the function "EM_EEPROM" will not be available.

If you look at the 'sct' code above, it seems to be caused by the load area being divided into LR_EM_EEPROM and LR_IROM1.

I want to know how to combine the areas of "LR_EM_EEPROM" and "LR_IROM1" to build.

Dear Receiver, 

After I read the app-note AN215656, I found there are 3 necessary ways that can let PSOC 6 dual core operate only in CM0+ .

#1. add "CORE=CM0P" in the "makefile".

#2. Modify the main.c file to remove any references to the HAL. Optionally, also remove any references to the BSP. (please refer to the attached file 1)

#3. Besides, I also found some differences between their main.c (please refer to the attached file 2)

👉for general initialization in main.c, we can see...

/* Initialize the device and board peripherals */
result = cybsp_init();
CY_ASSERT(result == CY_RSLT_SUCCESS);

👉for only operation in CM0+ initialization, we can see the main.c ...

/* Initialize system resources and peripherals. */
init_cycfg_all();

Could you kindly help me to check above #1, #2, and #3 ?!

Are above 3 items necessary modification points if I would like to use CM0+ only ?!

Anything I missed ? Please kindly guide me.

Thank you so much. 

Dear Receiver, 

I'm learning PSOC 6 recently. 

I found almost all sample codes are based on M4 only.

Do you have example codes only based on M0 + ?!

I would like to know how to design M0+ only. 

Thank you so much.

Hi 

I made custom BSP for CY8C6244AZI-S4D93.

I was trying to add DAC configuration using MTB but I think there are some problem with connection verification.

According to below diagram, direct output of DAC is able to connect with pin 6 of CTB port.

In this IC, CTB port is port 9 and pin 6 is not available.

so the other way to make output path of DAC is using buffer.

as you can see in following picture. When I set DAC output as buffered output, there is only one option that I could choose to use as DAC output path is v plus of opamp0.

but the indicator always shows me yellow light even I tried every other combination of connections.

of course I tried it after disabled all other peripherals even the debugging port. 

could you check this point?

I would like to confirm my observation when calling the Cy_Crypto_Core_ECC_SignHash() and Cy_Crypto_Core_ECC_MakeKeyPair() functions.  The Cy_Crypto_Core_ECC_MakeKeyPair() returns the public key (X & Y) in little endian format, same for the signature (R & S) returned by the Cy_Crypto_Core_ECC_SignHash() function.  I verified this by using Mbedtls to generate the public key from a private key created by Cy_Crypto_Core_ECC_MakeKeyPair().

PSoC 6 MCU: CY8C62x6,
CY8C62x7 Datasheet

I think that it was printed incorrectly in Address Map. Page 12 of 77

0xE010 0A000 – 0xFFFF FFFF Device Device-specific system
registers.

PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet (infineon.com)