PSoC™ 6

Dear Export.

Hello. I have a question as below.

I'm trying to use the emwin Driver provided in PSOC6. (pre included Driver at MTB IDE)

1. Is there a extra cost to implement the graphic function using the driver? Or is it available for free?

Please help.

Dears,

I would like to test FPU in PSOC6 in modus toolbox 2.4 environment

I installed CMSIS DSP and set all variables in makefile (DEFINES, INCLUDES, LDLIBS as noted in another posts like https://community.infineon.com/t5/PSoC-6/How-to-use-ARM-CMSIS-DSP-lib-in-ModusToolbox2-4/m-p/342494 ...) when VFP_SELECT=hardfp all source codes compiles ok and project seems to run normally but I still think that FPU is not used... So I would like also test with "software emulated" and compare execution time.

But when I set makefile variable VFP_SELECT=softfp or to empty value (as default) But now I got compilation errors like this "ld.exe: failed to merge target specific data of file...":

Linking output file mtb-example-psoc6-lptimer.elf
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_sin_f32.o) uses VFP register arguments, C:/Users/xxxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_sin_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_cos_f32.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_cos_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_mult_f32.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_mult_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_add_f32.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_add_f32.o)
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: error: ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_common_tables.o) uses VFP register arguments, C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf does not
c:/users/xxx/modustoolbox/tools_2.4/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: failed to merge target specific data of file ../CMSIS/DSP//Lib/GCC/libarm_cortexM4lf_math.a(arm_common_tables.o)
collect2.exe: error: ld returned 1 exit status
make[1]: *** [../mtb_shared/core-make/release-v1.9.1/make/core/build.mk:529: C:/Users/xxx/mtw/Low-Power_Timer/build/CY8CKIT-062-WIFI-BT/Debug/mtb-example-psoc6-lptimer.elf] Error 1
make: *** [../mtb_shared/core-make/release-v1.9.1/make/core/main.mk:434: secondstage_build] Error 2
"C:/Users/xxx/ModusToolbox/tools_2.4/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_MAKE_IDE_VERSION=2.4 CY_IDE_TOOLS_DIR=C:/Users/xxx/ModusToolbox/tools_2.4 -j12 all" terminated with exit code 2. Build might be incomplete.

What is going bed ? 

Best Regards

Radim

Hello,
I'm trying to program a hex file to CY8C6136 using Segger J-flash (V7.66a).

Q1. Which one should I choose from the list below in the Target Device Settings?

Q2. What is the difference between CY8C6xx6_CM4 and CY8C6xx6_CM4_sect256KB?

Q3. Should I only program to the M4 because it's single core?

Thanks and Regards,
YS

I would like to confirm my observation when calling the Cy_Crypto_Core_ECC_SignHash() and Cy_Crypto_Core_ECC_MakeKeyPair() functions.  The Cy_Crypto_Core_ECC_MakeKeyPair() returns the public key (X & Y) in little endian format, same for the signature (R & S) returned by the Cy_Crypto_Core_ECC_SignHash() function.  I verified this by using Mbedtls to generate the public key from a private key created by Cy_Crypto_Core_ECC_MakeKeyPair().

1. Created new modus application as follows : BSP > PSoC™ 62S2 > CY8CEVAL-062S2 > [NEXT]
: Select Application > Peripherals > MCUboot - Based Basic Bootloader > [CREATE]

2. Two project folders are created namely : MCUboot-Based_Basic_Bootloader.blinky_cm4 and MCUboot-Based_Basic_Bootloader.bootloader_cm0p

3. While building MCUboot-Based_Basic_Bootloader.blinky_cm4 we face 2 errors as mentioned below.

make[1]: *** [../../mtb_shared/core-make/release-v1.9.1/make/core/build.mk:557: CY_BUILD_app_postbuild] Error 126
make: *** [../../mtb_shared/core-make/release-v1.9.1/make/core/main.mk:434: secondstage_build] Error 2
"C:/Infineon/Tools/ModusToolbox/tools_2.4/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_MAKE_IDE_VERSION=2.4 CY_IDE_TOOLS_DIR=C:/Infineon/Tools/ModusToolbox/tools_2.4 -j4 all" terminated with exit code 2. Build might be incomplete.

11:46:12 Build Failed. 2 errors, 11 warnings. (took 7m:493ms)

providing the way to resolve this error and compile without these errors would be helpful.

Hi,

We are trying to port the existing firmware in PSOC Creator to ModusToolbox to make it available for the new chips.

However, the biggest challenge we are facing right now is the Analog Multiplexer that's not available in ModusToolbox as it is in PSOC Creator.

I'm wondering if there is any example on how to use the AMUX in ModusToolbox?

Any help will be much appreciated.

Thanks in advance.

GP

Dear Receiver, 

I practice "PSoC™ 6 MCU: MCUboot-based basic bootloader" by using the example code in the following GitHub link...

https://github.com/Infineon/mtb-example-psoc6-mcuboot-basic

I follow the steps and I can run boot, app (boot mode), and app (upgrade mode), separately.

But I feel confused about...

when I reset the board, there are no any response in the UART communication. Besides, LED blinking is also no response.

I think every time I reset MCU, it should enter boot mode. If no new image be found, it will enter app mode automatically.

in my test, it seems no any other response if I reset the board. I am sure boot code is in the CM0+ and app code is in the

CM4. Once I reset the board, boot code and app code seem disappear.

Could you please explain this phenomenon for me ?!

Thank you so much.

Hi.

I'm trying to use the HAL System Power Management library to put the CM4 to sleep. So far, I've had no luck, and as I have found too many times, there is very little documentation available, and no examples. What documentation exists (e.g. Architecture TRM) is unclear, even suggesting that only masked interrupts can wake up a sleeping CPU.

Here's the environment:

• PSoC 63 with BLE in a custom board.
  • MTB 2.3.0 
  • BSP 2.3.0
  • PDL 2.3.0
  • HAL 2.1.0
• CM4 and CM0+ running FreeRTOS
• Several peripherals in use (BLE, I2C, UART, SPI, RTC, TWPCM, etc.)

1. I registered four callbacks using cyhal_syspm_register_callback(). 
2. I call cyhal_syspm_sleep().
3. The four callbacks are called with state set to CYHAL_SYSPM_CB_CPU_SLEEP and mode set to CYHAL_SYSPM_CHECK_READY. All callbacks return true.
4. The four callbacks are called again with state set to CYHAL_SYSPM_CB_CPU_SLEEP, but this time mode set to CYHAL_SYSPM_BEFORE_TRANSITION.
5. The four callbacks are immediately called a third time with state set to CYHAL_SYSPM_CB_CPU_SLEEP, but this time mode set to CYHAL_SYSPM_AFTER_TRANSITION.

The first problem is that the CPU either doesn't sleep, or wakes up immediately. I disable the RTOS SysTick interrupt in one of the callbacks. I also disable several other peripheral interrupts, and turn off the BLE stack, none of which has made a difference. It's likely that some interrupt is firing, but I can't think of a good way to determine which is the culprit.

The second problem is that the stated behavior, namely that the callbacks are called on wakeup (CYHAL_SYSPM_AFTER_TRANSITION) in the reverse of the order in which they are called on sleep (CYHAL_SYSPM_CB_CPU_SLEEP) does not match the observed behavior.
Callbacks are always called in the same order, even when one of the callbacks returns false in response to CYHAL_SYSPM_CHECK_READY.

Has anyone successfully used cyhal_syspm_sleep() to put one of the CPUs to sleep?

Thanks,

-Nick