Zero Volt source for analogue peripherals

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Mrinal
Level 4
Level 4
First solution authored 50 replies posted 25 replies posted

Hi

I need to connect 0V to one of the inputs of an analogue comparator. Is there a way to connect VSS internally to the comparator. In the design wide resource there's logic 0, but I think this will still have a few tens of mV.

Is there a way to connect comparator to true zero or VSS?

Thank you

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1 Solution
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi Mrinal,

PSoC6 low power comp has connectivity to dedicated pins, Amuxbus and internal vref as shown in the image.

Vasanth_0-1649407634090.png

 

The internal connection to VSS is not supported in the architecture. You may have to connect the dedicated pin to GND if that is the requirement.

Best Regards,
Vasanth

 

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4 Replies
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi Mrinal,

PSoC6 low power comp has connectivity to dedicated pins, Amuxbus and internal vref as shown in the image.

Vasanth_0-1649407634090.png

 

The internal connection to VSS is not supported in the architecture. You may have to connect the dedicated pin to GND if that is the requirement.

Best Regards,
Vasanth

 

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Mrinal,

It is a pity that the PSoC6 doesn't have internal VSS connections available to the analogue components like the PSoC5 and PSoC3 have.

Now I could be wrong here ... why do you need VSS to supply to one of the inputs of your comparator?

Normally on a micro supplied by a single supply (3.3V in this case) ALL analog input voltages should be above VSS (=0V).  Placing VSS on one of the comparator inputs has no apparent value.

The two types of analogue comparators available to the PS0C6 can use either Vref (Bandgap Reference) or from the output of the Voltage DAC.

In general, a comparator reference input must be somewhere above VSS to be useful.

Len
"Engineering is an Art. The Art of Compromise."
Mrinal
Level 4
Level 4
First solution authored 50 replies posted 25 replies posted

Thank you for the reply.

 

We're using PSOC-6 chips for a solar inverter. Unfortunately the manufacturing had to be delayed due to reliability issue in one of the H-bridges.

The solution was to implement Cycle-by-cycle current limit with leading edge blanking. We are planning to implement it on three power stages. Therefore three blocks of cycle-by-cycle current limiter is needed. The software based limiter would take around 25us to activate and anything more than 10us resulted in occasional failure of MOSFETs if the output was shorted.

To mask the actual input to the comparator during leading edge blanking period, 0V or VSS needs to be relayed to the comparator, through an analogue MUX. The reference signal is around 40mV. Although LEB could be implemented on the output of the comparator, but may run into the risk of saturating the comparator output. The comparator we're using takes around 400ns to come out of saturation.

Initially the plan was to scan the reference voltage of the DAC through all the three current limiter comparators, that would provide a lot of flexibility to change the reference on the fly. But the DAC has +-10mV offset error and is probably not suitable for low voltage references.

Now we're using external analogue mux to relay VSS and current signal to external comparators. Only the digital logic is being implemented in PSOC.

 

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Mrinal,

Thanks for the clarification.

All the PSoCs are single-supply analogue devices.  This makes it non-trivial to read analogue voltages at or below 0V.   At best, you would need a voltage level shifter to bias the "zero-crossover" voltage at about 1/@ of the ADC voltage reference.

This is commonly done by using a signal transformer with a secondary with a center tap at a maximum output voltage at the ADC voltage reference @*2 and the center tap sourced with the VDAC output at the voltage reference.

This should work on many designs.  However there are some delays and potential voltage offsets which may be detrimental in your design.

Len
"Engineering is an Art. The Art of Compromise."
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