What is the minimum current needed by the PSOC6 in order to work?

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biniaming
Level 1
Level 1
First question asked First like given Welcome!

I want to use the PSOC 6 BlE using SOLAR CELL providing 1mA and 5V.

Is it possible?

Thanks

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1 Solution
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

biniaming,

The PSoC6 family of parts use a silicon geometry that can only tolerate 3.6V max.

Therefore the 5V solar cell needs to eventually be voltage regulated down to 3.3V max.

The simplest way to do this is to place a bulk capacitor (about 100uF or more) on the input to a LDO 1.8V regulator or a boost/buck switching mode regulator set to 1.8V.

As to the 1mA supply from the solar cell ...  this could be a problem.

With the bulk capacitance mentioned above, it provides energy storage when the PSoC is not using much such as during sleep.

In your design, the PSoC should be asleep at least 99% of the time.  In the proper sleep mode, the current draw can be as low as <5uA.  However, when in the Active power mode, the CPUs can easily draw 10mA or more.  If a BLE Tx or Rx operation is needed, it can take an additional 15mA.

This is why the bulk cap is needed.  During sleep (99% of the time) the cap stores the needed energy for when the device is active.  During the active phase, most of the energy is used.

Let's try an example.

Assumptions:

  • The solar cell gets enough energy through the day to supply 1mA @ 5V on the average.  If the sun or other light source is insufficient, the PSoC will not operate and will go through multiple power-up cycles.
  • For this example, a 100uF 6.3V bulk cap is used.
  • The maximum sleep load on VDDD is 5uA.  With a vreg ouput of 1.8V, the Rload on the vreg is about 360K ohms.
  • The maximum awake load on VDDD is 25mA.  With a vreg ouput of 1.8V, the Rload on the vreg is 72ohms.
  • A LDO voltage 1.8V regulator is used with a LDO of 0.2V.  Therefore the minimum usable voltage on the bulk cap is (1.7V+0.2V =)1.9V.  In this example I chose the ADI IC ADP121-1.8.
  • The active time needed for the project is 10ms every 1s.  This means the PSoC is asleep for 990ms.

Below is a LTSpice simulation of this circuit design.

Len_CONSULTRON_1-1668698153826.png

Here is the plot of vin, vout and the load on the vreg with the 10ms 25mA active current.

Len_CONSULTRON_2-1668698312858.png

Remember that if enough light is not available to charge the 100uF bulk cap, it will eventually deplete the charge on the cap below 1.9V causing the PSoC to power up reset when enough light is available.

If this were to occur, prevent any BLE operation for at least 1 wakeup period to allow the C1 and C2 caps to charge up.

 

Len
"Engineering is an Art. The Art of Compromise."

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2 Replies
Aashita_R
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 250 replies posted

Hi @biniaming ,

Can you please let us know the MPN of the device which you are using? Also, can you please elaborate your application a little more?

This will help us get more insights into the problem and help you with the correct advice.

Best Regards,

Aashita

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

biniaming,

The PSoC6 family of parts use a silicon geometry that can only tolerate 3.6V max.

Therefore the 5V solar cell needs to eventually be voltage regulated down to 3.3V max.

The simplest way to do this is to place a bulk capacitor (about 100uF or more) on the input to a LDO 1.8V regulator or a boost/buck switching mode regulator set to 1.8V.

As to the 1mA supply from the solar cell ...  this could be a problem.

With the bulk capacitance mentioned above, it provides energy storage when the PSoC is not using much such as during sleep.

In your design, the PSoC should be asleep at least 99% of the time.  In the proper sleep mode, the current draw can be as low as <5uA.  However, when in the Active power mode, the CPUs can easily draw 10mA or more.  If a BLE Tx or Rx operation is needed, it can take an additional 15mA.

This is why the bulk cap is needed.  During sleep (99% of the time) the cap stores the needed energy for when the device is active.  During the active phase, most of the energy is used.

Let's try an example.

Assumptions:

  • The solar cell gets enough energy through the day to supply 1mA @ 5V on the average.  If the sun or other light source is insufficient, the PSoC will not operate and will go through multiple power-up cycles.
  • For this example, a 100uF 6.3V bulk cap is used.
  • The maximum sleep load on VDDD is 5uA.  With a vreg ouput of 1.8V, the Rload on the vreg is about 360K ohms.
  • The maximum awake load on VDDD is 25mA.  With a vreg ouput of 1.8V, the Rload on the vreg is 72ohms.
  • A LDO voltage 1.8V regulator is used with a LDO of 0.2V.  Therefore the minimum usable voltage on the bulk cap is (1.7V+0.2V =)1.9V.  In this example I chose the ADI IC ADP121-1.8.
  • The active time needed for the project is 10ms every 1s.  This means the PSoC is asleep for 990ms.

Below is a LTSpice simulation of this circuit design.

Len_CONSULTRON_1-1668698153826.png

Here is the plot of vin, vout and the load on the vreg with the 10ms 25mA active current.

Len_CONSULTRON_2-1668698312858.png

Remember that if enough light is not available to charge the 100uF bulk cap, it will eventually deplete the charge on the cap below 1.9V causing the PSoC to power up reset when enough light is available.

If this were to occur, prevent any BLE operation for at least 1 wakeup period to allow the C1 and C2 caps to charge up.

 

Len
"Engineering is an Art. The Art of Compromise."
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