I'm trying to understand, via the Architecture TRM, Registers TRM, and the PDL documentation how the Trigger Mux's connect to the PWM Trigger inputs.
I can see that there are 2 Trigger Mux groups, 2 and 3, that connect into the TCPWM's. It looks like the TCPWMx_GRPy_CNTz_TR_IN_SEL1 register is used to select the trigger source for the START signal to the TCPWM. It looks like I can chose between 139 possible trigger choices per figure 25-3 in the TRM. It seems like I can pick the same trigger for each of the counters I might want to control. I want to understand in more detail what is happening
1) Trigger group 2 vs Trigger group 3, which one is used and where is this documented?
2) There are 28 outputs from those 2 trigger groups. How are they routed to the PWM's, where is this documented in the architecture or where is a register controlling this?
3) I cannot understand Table 29-2 in the TRM, there is no indication of what registers control this "selection"?
The PDL documentation shows that I can use Cy_TrigMux_SwTrigger to software trigger all my TCPWM's to START at the same time, but I am unclear how this occurs without understanding the mux connections from the Trigger mux to the individual TCPWM's. Please help my understanding.
And note, this is for the 6xx4 family which is the Ver 2 style of TCPWM and muxing.
On creating a project if you see the psoc6_0x_config.h file (present in mtb_shared\mtb-pdl-cat1\release-v2.3.1\devices\COMPONENT_CAT1A\include directory) you would notice enums for the different groups, (Group1 and Group 2 shown in the image below) and in the comments, you can see the different Trigger Outputs supported by each group.
Group2 output is used for triggering TCPWM 0 and Group3 is used for TCPWM 1.
Similarly, you can refer to the different structures for the possible trigger inputs to each of the Groups
2. "There are 28 outputs from those 2 trigger groups. How are they routed to the PWM's, where is this documented in the architecture or where is a register controlling this?"
Here do you mean what are the different possible inputs to the MUXs and what are outputs? As mentioned in the above point this information can be obtained from the config.h file. Kindly let me know if you were looking for some other information here.
Since this is for the Cy8C6xx4 parts (S4 variant), I would look at psoc6_04_config.h which has group 2 and group 3 input triggers shown in the enums, en_trig_input_tcpwm0_0_t and en_trig_input_tcpwm0_1_t
The outputs are in enums en_trig_output_tcpwm0_0_t and en_trig_output_tcpwm0_1_t
There are 14 outputs in each of those 2 groups as you show in your response.
1) How are those 14 mux outputs connected to the PWM trigger inputs? Does the register, TCPWMx_GRPy_CNTz_TR_IN_SEL1 select 1 of the 14 muxes? If so, the documentation is unclear as it states that the field is 5 bits (capable of 32 inputs) and the description states the field selects 1 of 256 trigger inputs as the start trigger. This is misleading.
2) I assume the input for a given mux in a mux group is selected by the PERI_TR_GRx_TR_CTLy where x is the group (2 or 3 for the PWM's), and y is the mux (0-13 for groups 2 and 3).
Ekta, based on all this information, can you explain how the code shown in the PDL documentation operates?
If you look at our example code in the PDL documentation, you see this:
#define GRP0_CNT0_NUM (0UL)
#define GRP0_CNT1_NUM (1UL)
#define GRP0_CNT2_NUM (2UL)
#define TCPWM0_TR_IN0 (0x40000200u) /* tcpwm.tr_in */
/* Set up input trigger start for all 3 counters to CY_TCPWM_INPUT_TRIG_1 */
Cy_TCPWM_InputTriggerSetup(TCPWM0, GRP0_CNT0_NUM, CY_TCPWM_INPUT_TR_START, CY_TCPWM_INPUT_LEVEL, CY_TCPWM_INPUT_TRIG_1);
Cy_TCPWM_InputTriggerSetup(TCPWM0, GRP0_CNT1_NUM, CY_TCPWM_INPUT_TR_START, CY_TCPWM_INPUT_LEVEL, CY_TCPWM_INPUT_TRIG_1);
Cy_TCPWM_InputTriggerSetup(TCPWM0, GRP0_CNT2_NUM, CY_TCPWM_INPUT_TR_START, CY_TCPWM_INPUT_LEVEL, CY_TCPWM_INPUT_TRIG_1);
/* Trigger through Software to start all 3 counters synchronously */
The first 3 lines to set up the input trigger to the 3 PWM's seems clear. We are setting up the START trigger to come from CY_TCPWM_INPUT_TRIG_1. If you look at our equates, it looks like CY_TCPWM_INPUT_TRIG_1 selects trigger input 1 to the PWMs. There are trigger inputs numbered 0 to 13, which I believe are referring to the 14 mux outputs from trigger mux group 2 (which are connected to Group 0 PWM's).
However, when we execute the SwTrigger, it would seem we are triggering the Group 2 output mux 0 based on the #define. But, we have not chosen mux output 0 in the InputTriggerSetup, we have chosen mux 1.
Please explain how/why this works. I would expect, based on the input trigger setup to the PWMs that we should be using TCPWM0_TR_IN1 to select the tcpwm.tr_in mux output to be triggered.
Ekta - Something seems to be wrong in our #defines! This works:
/* Set up input trigger start for all 3 counters to the undefined (?) mux selection of 16 */
Cy_TCPWM_InputTriggerSetup(PWM1_HW, PWM1_NUM, CY_TCPWM_INPUT_TR_START, CY_TCPWM_INPUT_RISINGEDGE, 16);
Cy_TCPWM_InputTriggerSetup(PWM2_HW, PWM2_NUM, CY_TCPWM_INPUT_TR_START, CY_TCPWM_INPUT_RISINGEDGE, 16);
Cy_TCPWM_InputTriggerSetup(PWM3_HW, PWM3_NUM, CY_TCPWM_INPUT_TR_START, CY_TCPWM_INPUT_RISINGEDGE, 16);
/* last output of the trigger mux goes to the 16th input of the input mux to the PWM??? */
...but we do not have a 17th mux input defined? I'm thinking the input mux to the PWM triggers looks like this:
0 = 0
1 = 1
2 = something I do not know
3 = 0'th output from trigger mux Group 2
16 = 13th output from trigger mux Group 2
Can we confirm this with the device architects.