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PSoC™ 6 Forum Discussions

Anonymous
Not applicable

Hello,

When I see PSoC6 Block diagram of figure1-1 in TRM, there are three MPUs.

They are CM4, CM0+ and Interconnect.

Whereas, when I see register TRM for MPU, there are four register of PROT_MPUx_MS_CTL.

Why are they different number?

Best regards,

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1 Solution
MeenakshiR_71
Employee
Employee
100 likes received 50 likes received 25 likes received

Hello user_474444345​,

Only three of the MPUs are usable for customers - MPU0 for CM0+, MPU1 for Crypto and MPU14 for CM4. The fourth MPU (MPU15) is meant for test controller, which is not usable for customers.

I see that is a mistake in our TRM document and will raise a defect ticket to get it rectified. Thanks for pointing it out.

Thanks,

Meenakshi Sundaram R

View solution in original post

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4 Replies
Bob_Marlowe
Level 10
Level 10
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System- and peripheral interconnect blocks are not a MPU.

Bob

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Anonymous
Not applicable

Hi Bob,

PSoC6 TRM description describe below.

An MPU that is implemented as part of the bus infrastructure. This type is found in bus masters such as crypto and test
controller. The definition of this MPU type follows the ARM MPU definition (in terms of memory region and access attribute
definition) to ensure a consistent software interface.

Best regards,

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Bad translation ambiguity, sorry

MPU = Microprocessor Unit

MPU=Memory Protection Unit

See here.

Bob

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MeenakshiR_71
Employee
Employee
100 likes received 50 likes received 25 likes received

Hello user_474444345​,

Only three of the MPUs are usable for customers - MPU0 for CM0+, MPU1 for Crypto and MPU14 for CM4. The fourth MPU (MPU15) is meant for test controller, which is not usable for customers.

I see that is a mistake in our TRM document and will raise a defect ticket to get it rectified. Thanks for pointing it out.

Thanks,

Meenakshi Sundaram R

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