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PSoC™ 6

easonlin
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Hey Sir,

MCU CY8C6347BZI-BLD54 is used as a CPU on our product and it has been produced for 50K-100K units. However, there are a few units (less than 1%) having boot-up issue after executing the process of secure boot. The failure symptoms are listed below:

1. Power up for several cycles and then finally it could boot up successfully. The cycle time of powering up can't be calculated. It's a random.

2.  Always fail to boot up so it becomes a brick.

3.  1 unit succeeds to boot up intermittently.

The eFuse of these units is burned successfully if we check the eFuse bit after the unit succeed to boot up. Thus, we can't read any debug information from the SWD port. Then some signal waveforms are captured and compared on both the situation of successful and fail boot-up. The main differences are

1. The power rail behavior of MCU_VIND2, MCU_VRF, and MCU_VBUCK1

2. The activated timing of SWDIO

Please refer to the attachment for more detail waveforms. We suspect this issue results from the process of eFuse burning but we don't have solid evidence to prove it. Thus, we need your thoughts and insights on this issue. It's getting more critical now due to the increasing production volume. Thanks.

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Rakshith
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Hi Eason, 

That is correct, by project I meant the firmware that you used to transition the device into SECURE mode.

Programming eFuses requires VDDIO0 to be 2.5V. Although it might work in some cases even when you use 3.3 V, we cannot guarantee the functionality and might result in bricking the device. 

Thanks and Regards,
Rakshith M B

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Rakshith
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Hi @easonlin

As only some devices are unable to boot up, it might not be an issue with the project implementation but just to be sure could you please share the project used to transition the PSoC 6 device to SECURE lifecycle? If possible, can you please share the steps that you followed too?

Also, can you confirm that you have used 2.5V during eFuse writes? 

Thanks and Regards,
Rakshith M B
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easonlin
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Hey @Rakshith , 

1. Is the "project" you mentioned the "FW code" that we used?

2. The 3.3V is used during eFuse writes. Will this create any problem? Although, we know 2.5V is requested during eFuse writing process suggested in the spec, we did some bench test to do eFuse burning with 3.3V applied and we didn't see any issue. Not sure if the sample size is not big enough so we didn't encounter any issue during bench test? Have you ever encountered any eFuse issue due to incorrect voltage applied during eFuse burning process?

 

Thanks,

Eason

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Rakshith
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Hi Eason, 

That is correct, by project I meant the firmware that you used to transition the device into SECURE mode.

Programming eFuses requires VDDIO0 to be 2.5V. Although it might work in some cases even when you use 3.3 V, we cannot guarantee the functionality and might result in bricking the device. 

Thanks and Regards,
Rakshith M B
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easonlin
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Hey Rakshith,

  1. The "efuse programming" FW routine is attached. Please help to review it and feel free to provide any comments for us. Since I am an electrical engineer, not sure if the FW routine is what you want. If not, please feel free to let me know and I could try to find out the proper file that you want.
  2. By the way, the schematic design of MCU power rail is also attached. You mention that "ONLY" VDDIO0 should be 2.5V. I am wondering in our design VDDIO0, VDDIO1 and VDDIOA are connected together, and could this connection cause any problem during the secure boot process? Also, 1.8V is also supplied to VDDD and VDD_NS during secure boot process, would this cause any problem? 

Thanks.

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Rakshith
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Hi @easonlin

In this case, connecting the VDDIO lines to 2.5 V should still work as they can be independent of each other. Additionally, I could not find any information regarding the capacitors on the power lines. Please ensure that you have followed the hardware design guidelines as mentioned on page 5 of the PSoC 6 Hardware Design Considerations document. 

You will also find information regarding eFuse programming in the same document on page 8.

Thanks and Regards,
Rakshith M B
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easonlin
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Hey @Rakshith,

All caps are added following the recommendation in the design guideline. Thanks.

easonlin_0-1641141019597.png

Thanks,

Eason

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Raj_JC
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Hi @easonlin,

Following are the recommendations for the attached schematic:
1) Connect ferrite bead in series with the supply to the VDDA. Also, connect 10uF and 0.1uF capacitor at VDDA.
2) Short the VDDIOA pin to the VDDA.
3) MCU_VDDR must be connected to VDCDC & VRF with an inductive filter in series.
4) Short VRF and VDCDC and place 10uF capacitor close to the VDCDC.
5) Ensure VDD_NS has a filter in series.
6) VCCD doesn’t require the 1uF capacitor.

All the above recommendations are mandatory but this should not affect the boot-up of the device. Please, try to follow the suggestion given by @Rakshith to use 2.5V. 

Please, let us know if you need further clarification.

Thank you
Best Regards

Raj Chaudhari

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