TCPWM interrupt on CM0+

[rushikeshmunde]

Hi, 

I am used PSoC 6 PROTO Kit & I have initialized tcpwm counter using Device Configurator.  I want to use it as interval timer, 

when I run it on CM4 core, it works fine, I get the delay as expected. But I want to use the interval timer on CM0+ core. Since the device configurator generates code in mtb shared folder, I can initialize the timer on CM0+ with no compilation error, but the interrupt service routine never gets called, and therefore the timer doesnt work. 

Can TCPWM interrupt be used on CM0+ ? 

How can I set tcpwm interrupt for CM0+ core ?

Thanks & Regards 

Rushikesh 

[Ekta_N]

Hello @rushikeshmunde 

When creating an application for a CM0+ device you need to perform certain additional steps as mentioned in section 4.1.1 Creating the CM0+ CPU Application of the PSoC 6 MCU Dual-CPU System Design.

Could you please let me know if you are following these steps?

In case you are making the same observation even after following these steps kindly attach your project here so that I can have a look at the configuration.

Best Regards
Ekta

[rushikeshmunde]

Hi, 

I have referred to the document and followed those steps at the time I created project.

After that I initialized timer using device configurator. 

I have attached the project for your reference. 

[ClarkJarvis]

@rushikeshmunde ,

Here is an additional Application Note that may be of assistance (AN217666 - PSoC 6 MCU interrupts)

Specifically when creating the Interrupt config structure for the CM0 project, you need to specify the peripheral interrupt source (in this case the TCPWM specific one) as well as the CM0+ NVIC IRQ that you wish to map the interrupt source to.

Refer to the code snippet below:

/* Initialize and Enable Timer interrupt with the NVIC */
cy_stc_sysint_t irqCfg_Timer = {
     .intrsrc=NvicMux2_IRQn,
     .cm0psrc=tcpwm_1_interrupts_4_IRQn,
     .intrPriority = 3
};
Cy_SysInt_Init(&irqCfg_Timer, MyTimerISR);
NVIC_ClearPendingIRQ(NvicMux2_IRQn);
NVIC_EnableIRQ(NvicMux2_IRQn);

In this section of code, tcpwm_1_interrupts_4_IRQn is mapped to NvicMux2_IRQn

The initialization function initialize the interrupt register and associated the ISR to the function specified.

The code then clear and enabled the CM0+ interrupts using the NVIC_xxxx APIs and specifying the CM0+ interrupt IRQ (in this case NvicMux2_IRQn).