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notAnumber
Level 1
Level 1
50 sign-ins 5 questions asked 5 replies posted

Hello!

I am trying to setup a watchdog timer on my PSoC 6 board, CY8PROTO-062-4343W.

This using the cy_pdl.h library. I followed the steps in the PSoC 6 PDL github page under watchdog to set it up.

But the problem I have is that I don't get a reset of the system when the interrupt occurs. And I don't understand why?

I found one example on the infineon github page.

https://github.com/Infineon/Code-Examples-for-the-ModusToolbox-PSoC-6-SDK/blob/mt1.1/CE220060_PSoC6_...

But its 4 years old so maybe its outdated, because I couldn't get that to work.

The example projects on the project creator are all using cyhal, which I can't do in my project.

Why can't I get it to work?

Here is how I initializes the WDT.

 

// Initializes WDT.
void InitializeWDT()
{

	Cy_SysClk_IloEnable();
	
	Cy_WDT_Unlock();
	
	Cy_WDT_Disable();
	
	Cy_WDT_SetMatch(0);

	Cy_WDT_SetIgnoreBits(0);

	Cy_WDT_Enable();

	Cy_WDT_Lock();
}

 

 

See attached .c file for full project.

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Ekta_N
Moderator
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750 replies posted First like given 250 solutions authored

Hi @notAnumber 

I made some changes in the code you provided and could get the code working. Attaching  main.c file for the same.

Ekta_0-1680067353931.png

Hope this helps.

Best Regards
Ekta

 

 

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Aashita_R
Moderator
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50 likes received 100 solutions authored 250 replies posted

Hi @notAnumber ,

As mentioned in page no 264 of PSoC 6 Architecture TRM,  the timer can generate an interrupt on match and a reset
event on the third unhandled interrupt. 

Aashita_Raj_0-1679998400945.png

When the counter value (WDT_CNT register)equals the match value stored in MATCH bits [15:0] of the WDT_MATCH register, an interrupt is generated. The match event does not reset the WDT counter and the WDT keeps counting until it reaches the 16-bit boundary (65535) at which point, it wraps around to 0 and counts up. The match
interrupt is generated every time the counter value equals the match value.


The WDT_MATCH bit of the SRSS_INTR register is set whenever a WDT match interrupt occurs. This interrupt must
be cleared by writing a ‘1’ to the same bit. Clearing the interrupt resets the watchdog. If the firmware does not clear the interrupt for two consecutive occasions, the third interrupt generates a device reset.

I hope this helps. Please add here in case of any further query.

Best Regards,

Aashita

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Ekta_N
Moderator
Moderator
Moderator
750 replies posted First like given 250 solutions authored

Hi @notAnumber 

I made some changes in the code you provided and could get the code working. Attaching  main.c file for the same.

Ekta_0-1680067353931.png

Hope this helps.

Best Regards
Ekta

 

 

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