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What is the guideline for setting oversample ?
Should I pay attention to the actual data rate ?
For example, under the following conditions, Actual data rate is 2000 kbps only when oversample is "5".
・Clk_Peri : 50[MHz]
・Data rate : 2000[kbps]
When [Clk_Peri / (Data rate * oversample)] is divisible, Actual data rate will be the value as configured.
example) 50 [MHz] / (2000[kbps] * 5) = 5 with a remainder of 0.
Is my idea correct? Also, please tell us about the basis for this.
Solved! Go to Solution.
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Yes, you should.
When you decide OVS, you consider the actual data rate displayed on component window.
Note that this actual data rate displayed on component window is just estimation. For more precise data rate, you should consider the delay calculation, as well.
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Regarding following thread, the bit rate is calculated with:
Bit Rate = Input Clock/OVS
Where “Input Clock” is internal clock for SPI module, and OVS is the oversampling setting in SCB_CTRL register.
While, according the SPI component datasheet “SPI (SCB_SPI_PDL) : 002-19376 Rev. *B”, the Actual Data rate is calculated with:
tROUND_TRIP_DELAY = tSCLK_PD_PCB + tDSO + tMISO_PD_PCB + tDSI
- tSCLK_PD_PCB is the PCB path delay of SCLK from the pin of the master device to the pin of the slave device.
- tDSO is the time from the slave receiving the SPI clock edge at the pin to the MISO changing at the pin
- tMISO_PD_PCB is the PCB path delay of MISO from the pin of the slave device to the pin of the master device.
- tDSI is the setup time of MISO signal to be sampled correctly by the master.
tDSO and tDSI are specified in datasheet.
When tROUND_TRIP_DELAY is calculated, the maximum communication data rate between master and slave can be defined:
fSCLK(max) = 1 / (2 * tROUND_TRIP_DELAY)
in this case, the master samples the MISO signal one half SCLK period after the driving edge.
When the master can sample the MISO signal, one full SCLK period after the driving edge (late MISO sampling), the communication data rate is doubled and calculated as follows:
fSCLK(max) = 1 / tROUND_TRIP_DELAY
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Could you tell me the specific case?
I read this explanation in the component datasheet, but I don't understand.
Using PSoC 61, if Data rate is 2000 [kbps] and Oversample is 5,
-Input Clock = 2000[kbsp] * 5 = 10[MHz]
-tDSO = TDSO_EXT+3 * Tscb
= 20 + 3 * 100(Input Clock[ns])
= 320[ns]
-tDSI = 5[ns]
How are tSCLK_PD_PCB and tMISO_PD_PCB calculated and the actual data rate is 2000 kbps?
Also, please let me know if there is a mistake in my calculation or if you need any other information.
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Sorry for making you confused by my response #1.
The Actual data rate displayed in the component window is just Fscbclk/ OVS
2000 kbps = 10 MHz/5.
So, Actual data rate displayed in the component window doesn’t use round trip delay in the calculation.
The Actual data rate displayed in the component window is just Fscbclk/ OVS
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>The Actual data rate displayed in the component window is just Fscbclk/ OVS
Really?
In the case that oversample is "6";
Fscbclk = 2000 [kbps] * 6 = 12 [MHz]
In your formula, 12/6 = 2000 [kbps], but the actual display is 1666.667[kbps] in component window.
According to my research, "Data rate = actual data rate" is valid only when [Clk_Peri / (Data rate * oversample)] is divisible.
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- Fscbclk = 10MHz
- OVS = 6
Actual date rate = Fscbclk/ OVS = 10MHz/6 = 1666.667 (kbps)
This Actual date rate is displayed in component window.
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I see. I misunderstood Fscbclk. Fscbclk is Nominal Frequency.
I also understood how to calculate the actual data rate. Thank you.
Back to the first question, should I consider only actul data rate when deciding oversample?
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Yes, you should.
When you decide OVS, you consider the actual data rate displayed on component window.
Note that this actual data rate displayed on component window is just estimation. For more precise data rate, you should consider the delay calculation, as well.
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Thank you for your support.