- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I have the PSoC 6 connected to four MX25(https://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6... )external flash chips over SPI.
When I connect any one, or two chips to the psoc I can read and write great. When I connect 3 or more I am unable to read or write any data to any of them. Everything shows up incorrectly.
Any idea what could be causing this? I have tried adding pull up resistors to the chip selects. Also all of the chips work separately, and work in any combination of two.
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ryan,
Then, please check the SPI bus with an oscilloscope.
* Is only one CS# asserted from three or four devices?
If more than one device is selected by CS#, SO has unexpected signal.
* Does SCLK have eight pulses per a byte?
PSoC should be the only one driver for SCLK signal.
* Does SI have expected bit pattern?
SI is also driven by PSoC only.
Regards,
Noriaki
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It seems that the load capacitance on the SPI bus increased by increasing the number of devices connected on the bus.
Please reduce the SPI clock frequency. All devices can be accessed if the load capacitance is the root cause.
Regards,
Noriaki
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Noriaki,
I tried reducing the clock speed and still no luck. Any other suggestions?
Thanks,
Ryan
On Wed, Aug 19, 2020 at 11:55 PM Noriaki Tanaka <
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ryan,
Then, please check the SPI bus with an oscilloscope.
* Is only one CS# asserted from three or four devices?
If more than one device is selected by CS#, SO has unexpected signal.
* Does SCLK have eight pulses per a byte?
PSoC should be the only one driver for SCLK signal.
* Does SI have expected bit pattern?
SI is also driven by PSoC only.
Regards,
Noriaki
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi RyWi_4724536,
Did you get a chance to look at NoriakiT_91-san's suggestions? Please give us more insight (project, schematic, waveform etc) to debug this issue and help you better.
Regards
Bragadeesh
Bragadeesh