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vapa_4242486
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I'm using PSOC 6 BLE pioneer board for development. I'm trying to generate 9 pulse output simultaneously, for that I have created 9 pulse generator. All of them will be triggered by one button. I'm only able to generate 4 pulse outputs, beyond that I'm getting this error

```

--------------- Build Started: 05/24/2019 11:21:33 Project: test_timer, Configuration: ARM GCC 5.4-2016-q2-update Debug ---------------

cydsfit.exe -.appdatapath "C:\Users\vaishali\AppData\Local\Cypress Semiconductor\PSoC Creator\4.2" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p "C:\Users\vaishali\Documents\PSoC Creator\Workspace01\test\test_timer.cydsn\test_timer.cyprj" -d CY8C6347BZI-BLD53 -s "C:\Users\vaishali\Documents\PSoC Creator\Workspace01\test\test_timer.cydsn\Generated_Source\PSoC6" -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE

Elaborating Design...

HDL Generation...

Synthesis...

Tech Mapping...

Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWCLK_TCLK(0) at location P6[7] prevents usage of special purposes: TCPWM[3].line_compl. (App=cydsfit)

Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWCLK_TCLK(0) at location P6[7] prevents usage of special purposes: TCPWM[19].line_compl. (App=cydsfit)

Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWDIO_TMS(0) at location P6[6] prevents usage of special purposes: TCPWM[3].line. (App=cydsfit)

Info: plm.M0038: The pin named CY_CPUSS_SWJ_SWDIO_TMS(0) at location P6[6] prevents usage of special purposes: TCPWM[19].line. (App=cydsfit)

Analog Placement...

Analog Routing...

Analog Code Generation...

Digital Placement...

Digital Routing...

Error: rtr.M0004: E1217: Failed to route all nets; unable to resove overuse

Error: rtr.M0004: Error routing design: Routing Failed (11)

Dependency Generation...

Cleanup...

Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)

--------------- Build Failed: 05/24/2019 11:21:55 ---------------

```

Below is the screenshot of the pulse generator. From the diagram you can see the pulse generator is triggered from the button, which is the common signal for all the rest 8 pulse generator. I will attach my project file for more clarity of the problem.

I would like to know is there anyway I can get rid of the problem or Maybe I'm doing something wrong. Any help would be appreciated. 

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1 Solution

Hi,

The Problem is caused by using too many of the TCPWM trigger and/or UDB trigger signals within the design.

If you have a look in the Architecture TRM ("Trigger Multiplexer Block" Chapter [page 201]) there are limited amounts of trigger signals per peripheral:

- For the TCPWM there are only 16 different trigger signals that can be used to route the TCPWM overflow signals.

- From those only 8 can be routed to the UDBs.

pastedImage_14.png

https://www.cypress.com/file/385621/download

There are also some points where you can reduce the amount of trigger signals needed. For example

- on the pages 6 to 9 you could use the TCPWM ability to swap its period on TC, that way you save one trigger signal and one TCWPM per page. In addition to the periodic swap, you could also use PWM_line signals as clock for the FlipFlop. In that case there is no trigger signal used for the clock of the FlipFlop at all.

pastedImage_9.png

Also on the first 5 pages there could be some trigger signals be saved by using the TCPWM line signals.

Achim

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9 Replies
AnkitaS_51
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Hi,

We will need the project to understand the issue. Please share the project.

Most probably it's a routing issue.

Thanks,

Ankita

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Hi Ankita,

I just edited my question with more details, please refer to it again.

Thanks.

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Hi ,

I cannot open the project attached in Creator 4.2.

Can you please right click the project in PSoC Creator 4.2 and then choose Archive, then use Complete option.

Then the Archive of the project will be created in Archive Folder of project.

Please attach that Archive of the project here.

Thanks,

Ankita

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Okay.

I have attached archive zip file here. Please refer.

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This design as such without any change cannot be routed.

Now , the question is why it is happening.

So PSoC Creator has a router which takes your logically connectivity and maps it to the physical chip, which is good.  That said, since you're defining things logically, you can make a design that won't route.  It isn't detectable until the router runs, but like I said, routing is a hard problem, so that is deferred until you build.  (If the router ran every time you made a change, you wouldn't be able to use the tool, it would simply be too slow.)  Your logical design does have some DRCs, but that doesn't mean the design is feasible.  In some cases the physical block simply doesn't connect.  In others you've put too much in the design to have it fit.

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Yes, I have already seen this answer here Error: rtr.M0004: E1217: Failed to route all nets; unable to resove overuse 

But this doesn't tells me what exactly is the issue or how can it be fixed, if like you said my design is feasible. Hope to get an insight on this. Any help would be appreciated.

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Note that even though the logic used is less than 100% if you check the .rpt file in Results tab, the tool is not able to find routes for all of the logic due to densely packed design .

I have tried to ask the tool to optimize for area(Build settings-->Synthesis-->Optimization goal).

I tried unlocking the pins and removing certain gates and Flip flops, but nothing is helpful.

This  appears to me as basically routing constraint occurring in UDB thus it is unable to have valid placement.

You have to optimize or change the design.

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Hi,

The Problem is caused by using too many of the TCPWM trigger and/or UDB trigger signals within the design.

If you have a look in the Architecture TRM ("Trigger Multiplexer Block" Chapter [page 201]) there are limited amounts of trigger signals per peripheral:

- For the TCPWM there are only 16 different trigger signals that can be used to route the TCPWM overflow signals.

- From those only 8 can be routed to the UDBs.

pastedImage_14.png

https://www.cypress.com/file/385621/download

There are also some points where you can reduce the amount of trigger signals needed. For example

- on the pages 6 to 9 you could use the TCPWM ability to swap its period on TC, that way you save one trigger signal and one TCWPM per page. In addition to the periodic swap, you could also use PWM_line signals as clock for the FlipFlop. In that case there is no trigger signal used for the clock of the FlipFlop at all.

pastedImage_9.png

Also on the first 5 pages there could be some trigger signals be saved by using the TCPWM line signals.

Achim

Thanks Achim, was able to solve the issue after reading your answer. I refferred to the TRM and found out I can easily achive my goal with a timer and PWM only. My design is much more simpler now. Thanks.

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