Publishing a custom component (with UDB, etc.) as an undisclosed Object

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UrPl_1236626
Level 4
Level 4
10 likes given First solution authored 50 replies posted

Hi,

is there a way to publish a hardware component which "hides"  the actual design entry to some degree,

besides the Verilog obfuscation.

BR Uros

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1 Solution

BR Uros,

I've created a number of custom components so I'm familiar with many of the elements that go into a component.  However I've never needed to "hide" the custom component.  Therefore my steps below have never been tested.  I'm posting an idea.

Theoretically, it should be possible to create a partial custom (hidden) component.  I'm assuming you already have a working custom component.  I'm also assuming you are an advanced user of Creator so I'm not going into tremendous detail in the descriptions below.

I've never done this but here is my best guess of the steps needed to hide a partial TopDesign implementation:

  1. Create a working project with your custom component.
  2. Make sure ALL logic you want to hide is INSIDE the component.  This will be needed for the next step to make sense.
  3. Using the DWR/Directives tab, make all the directives for your custom component internal sub-components 'hard'.  This fixes the assignments of UDB, Macrocell, Control/Status Regs, etc.  This is needed for the next step.
  4. Because you 'hard' assigned the UDB assignments in Step 3, you need to determine the register addresses and pre-set values that Creator assigns.  This info will be needed for Step 6.3.  This can be done using the PSoC5 TRM and stopping the code in debug mode at main().  You can use the Memory monitor window to read these.
  5. Perform a complete rebuild of the project and save the text generated in the "Output" window.  This will be needed in Step 7.3.5
  6. Archive your project & component(s) for later updates by you but not your customer.  This has ALL the IP in a easier human-alterable form.
  7. Make a cloned copy of this project for your customer but make the following changes:
    1. In your custom component(s) KEEP the following:
      1. The API folder with all the .c, .h, .s files.  These will probably be needed for the project SW to call the internal functionality of your component.
      2. The component symbol file (<componentname>.cysym).  This is still used inside the TopDesign file you pass on to your customer.    This will be a 'dummy' symbol for user visualization of the signal flow.
      3. Any files in the "Custom" directory (*.cs)  that implements the user interface for configuring the component parameters. (If you have them.)
    2. In your custom component(s) DELETE the following to erase the user-modifiable design files:
      1. The component schematic  (<componentname>.cysch). 
      2. If you defined your UDB logic with the UDB editor, delete the (<componentname>.cyudb) file.
      3. If you defined your UDB logic using a Verilog, delete the (<componentname>.v) file.
      4. (<componentname>.cysch).
    3. Now that you have the info collected in Step 4:
      1. You need to create a .c file with the const values (to store in FLASH) for each of the PSoC5 UDB registers and datapaths you need to 'force load'.
      2. Create a C function call (Load_customUDBs()) to load the above constant values into the same registers you in the working version.
      3. Call the function Load_customUDBs() almost immediately after main().  This should load the custom component settings.
      4. Hopefully at this point you have not tried rebuild yet.  A rebuild will probably fail at this point.  It'll complain that something is missing.  (I could be wrong here?)
      5. Instead of a rebuild of the application you will have to use the CLI commands to compile and link.  I suggest using the saved text from Step 5.  This can be modified to create a batch build.   But delete the execution line that builds the application from the TopDesign info.  This would be the line that starts out with "cydsfit.exe ..."

This a lot of info to go through.  Good luck.

  1.  
Len
"Engineering is an Art. The Art of Compromise."

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9 Replies
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

BR Uros,

I'm assuming you are acting as a contractor to another company and you want to provide a "completed" project to while keeping some of your IP "less obvious" to this company.

What tools are you using to create this component?  UDB editor?  DataPath Config Tool?

Theoretically the most obscure you can provide is a FLASH data file that loads the UDB configuration data at boot time.  The data will be binary and have no easier human readable format.  This is the best level of obfuscation you can provide.  The source code (.c, .h, .s) files can still be modified by others.

In this  FLASH UDB loading file method, you can modify the UDB component if you have the original TopDesign.  The TopDesign you provide to the customer would have to be blank except for allocation of the GPIO pins which need to be locked.

Providing the Verilog would be better for modifying the design however it contains significantly more human-understandable information of the inner workings of the component functionality.

Len
"Engineering is an Art. The Art of Compromise."
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Hi Len,

actually it is a bit of logic and UDBs, drawn in sch with udb editor. The logic is the problem as it is not fully predictable where it maps in the final design.

BR Uros

BR Uros,

I have some ideas but before I share I have questions.

What parts of the Creator design are you planning on sharing with the customer?

  • The SW files?
  • The TopDesign file?
  • Verilog Design file for your custom component?
Len
"Engineering is an Art. The Art of Compromise."
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Basically everything, the only exception would be one little custom "logic" which includes logic + UDB.

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BR Uros,

If you're willing to give away the Verilog file of your custom logic component, you just need a component symbol with the Verilog reference in it.

However, the Verilog, although somewhat complex, can be fairly easily reversed-engineered by an advanced person with knowledge of this VHDL language.

If you don't want to distribute the Verilog, it should be possible but definitely more complicated set of steps.

Len
"Engineering is an Art. The Art of Compromise."
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Yes that's the point, how to distribute "a binary" of the programmable logic, which contains logic + udb.

In what direction would be your idea?

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BR Uros,

I've created a number of custom components so I'm familiar with many of the elements that go into a component.  However I've never needed to "hide" the custom component.  Therefore my steps below have never been tested.  I'm posting an idea.

Theoretically, it should be possible to create a partial custom (hidden) component.  I'm assuming you already have a working custom component.  I'm also assuming you are an advanced user of Creator so I'm not going into tremendous detail in the descriptions below.

I've never done this but here is my best guess of the steps needed to hide a partial TopDesign implementation:

  1. Create a working project with your custom component.
  2. Make sure ALL logic you want to hide is INSIDE the component.  This will be needed for the next step to make sense.
  3. Using the DWR/Directives tab, make all the directives for your custom component internal sub-components 'hard'.  This fixes the assignments of UDB, Macrocell, Control/Status Regs, etc.  This is needed for the next step.
  4. Because you 'hard' assigned the UDB assignments in Step 3, you need to determine the register addresses and pre-set values that Creator assigns.  This info will be needed for Step 6.3.  This can be done using the PSoC5 TRM and stopping the code in debug mode at main().  You can use the Memory monitor window to read these.
  5. Perform a complete rebuild of the project and save the text generated in the "Output" window.  This will be needed in Step 7.3.5
  6. Archive your project & component(s) for later updates by you but not your customer.  This has ALL the IP in a easier human-alterable form.
  7. Make a cloned copy of this project for your customer but make the following changes:
    1. In your custom component(s) KEEP the following:
      1. The API folder with all the .c, .h, .s files.  These will probably be needed for the project SW to call the internal functionality of your component.
      2. The component symbol file (<componentname>.cysym).  This is still used inside the TopDesign file you pass on to your customer.    This will be a 'dummy' symbol for user visualization of the signal flow.
      3. Any files in the "Custom" directory (*.cs)  that implements the user interface for configuring the component parameters. (If you have them.)
    2. In your custom component(s) DELETE the following to erase the user-modifiable design files:
      1. The component schematic  (<componentname>.cysch). 
      2. If you defined your UDB logic with the UDB editor, delete the (<componentname>.cyudb) file.
      3. If you defined your UDB logic using a Verilog, delete the (<componentname>.v) file.
      4. (<componentname>.cysch).
    3. Now that you have the info collected in Step 4:
      1. You need to create a .c file with the const values (to store in FLASH) for each of the PSoC5 UDB registers and datapaths you need to 'force load'.
      2. Create a C function call (Load_customUDBs()) to load the above constant values into the same registers you in the working version.
      3. Call the function Load_customUDBs() almost immediately after main().  This should load the custom component settings.
      4. Hopefully at this point you have not tried rebuild yet.  A rebuild will probably fail at this point.  It'll complain that something is missing.  (I could be wrong here?)
      5. Instead of a rebuild of the application you will have to use the CLI commands to compile and link.  I suggest using the saved text from Step 5.  This can be modified to create a batch build.   But delete the execution line that builds the application from the TopDesign info.  This would be the line that starts out with "cydsfit.exe ..."

This a lot of info to go through.  Good luck.

  1.  
Len
"Engineering is an Art. The Art of Compromise."

Thank you for your idea, will have a deeper look.

UDB cannot really be hidden, as the meaning of the bits are seen from the datapath config tool, so it's mainly more about the logic surrounding the UDB, but the logic cannot be fixed.

Besides Verilog obfuscation, an option would be to do pre-synthesis into RTL design (i.e. possibly Yosys could do the job), which at the same time makes code less readable. Full hiding it is of course never possible, and reverse engineering is possible.

The use of this could be also for some open source projects, where author wish to keep some concepts while giving away the implementation. Maybe lets say it is more in this context.

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Actually the all the UDB and datapath logic can be fixed (or as a call 'hard').

Here is a link to a tool create by a very smart fellow UDB enthusiast (to pull out the UDB and datapath info from a Creator project and to allow this info to be moved to a ModusToolbox project.

Link to discussion thread:  ModusToolbox-General/How-do-I-create-a-custom-UDB-solution-in-the-Modus-toolbox 

Link to the tool: udb-porting-tool-export-the-udb-configuration-from-psoc-creator-to-modustoolbox 

As you probably are aware, ModusToolBox doesn't have support for The UDB architecture creation and support.   This brilliant user reads the UDB and datapath info from a Creator program and creates a binary file with this info (obfuscation).  Then he provides a function to load this information in your ModusToolBox main() function.

I have verified on a few experiments that this method has worked for me moving the info to MTB.  I suspect, that the same info and loading function may work inside Creator with a 'blank' TopDesign file and removed custom component files.  (Haven't tested that theory.) 

If I'm correct, you can obfuscate ALL the logic.  All the design logic is fixed and can only be changed with the TopDesign and custom component files present.  Once you make the needed changes, you use the tool I mentioned and replace a blank TopDesign file and remove a component files AND provide ALL the files in the "Generated_Source" directory.  The "Generated_Source" directory contains all the source files and headers needed to call functions of the "hidden" components as well as the Cypress-supplied files such as those in the cy_boot directory etc.

I think this is possible.

If you want, you can provide more obfuscation, but it requires giving the customer only a .hex file.

Len
"Engineering is an Art. The Art of Compromise."
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