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PSoC™ 6 Forum Discussions

psoc_student
Level 3
Level 3
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Hello

I'm delveloper who using psoc6 wifi-bt pioneer kit.

I have question about RTC.

I know RTC is using ILO, so I know error is +-10%.

I want reduce error, But I can't use external crystals.

If so, can you modify it in software to reduce errors?

I'd like to know if there's a way.

Thank you for your reply.

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1 Solution

psoc_student,

Do you have any data or examples to refer to?

If you were working on a PSoC5LP, I would say 'yes'.  I do not have an example on a PSoC6 which as a different clocking structure.

However the principles for the method are the same.

You need to use a more accurate clocking source as your reference to trim the ILO.

You're using the PSoC6 WiFi-BT pioneer kit.   This kit comes with a watch crystal on-board.   You indicated you were going to use the IC but not the kit in production.

I don't know the PSoC6 WiFi-BT kit very well but if you're going to communicate with the WiFi or the Bluetooth resources, you will need a crystal-based clock somewhere in your design.

Once you identify this much more accurate clock, you will need to feed this clock (or a lower division) into a counter with capture capability.   The size of the counter needs to have enough bits of resolution to capture two ILO events.

For example, if your reference clock is 48MHz and the ILO is ~32.768KHz you'll need at least a 16-bit counter.

Connect the your reference clock to the "Clk" input and the ILO clock to the "Capture" input.

Set up the counter as continuous free-running.

(Note:  If you don't want to use HW Capture, you can connect a SW isr to the ILO clock.)

The goal is that the counter value (or capture count) differences between each ILO rising edge should be CLKref/CLKilo = 48MHz/32768Hz = 1464.84 => 1465 counts.  

Algorithm

If the count differences are greater than 1465 then ILO is too slow.  Trim the ILO to raise the clock frequency by one trim value.  

If the count differences are less than 1465 then ILO is too fast.  Trim the ILO to lower the clock frequency by one trim value.  

Repeat the algorithm until you're within one or two counts of the target count difference or you are starting to trim 'oscillate'.

Once you have a working algorithm, you need to decide if this is going to be a continuous trim operation or it is performed occasionally (to adjust for operational temperature differences) or if it is one-time production (one-and-done).    If it is a one-and-done calibration, you will ant to store the trim offset factors into EEPROM, so that if a power interruption occurs, you can reload these trim factors from EEPROM back into the ILO trim registers.

Notes on implementation

Using the counter in continuous mode means that the counter value will wrap.   You need to take this into account when calculating the count difference.   By increasing the counter resolution to 32-bits the wrapping will occur much less often.

The ILO trimming only allows up to a +/- 1.5% accuracy.   Therefore even if your reference clock source is +/- 0.001% you will be limited as to the best accuracy of ILO.

Also consult with the ILO documentation.  Apparently there is a Clock Measurement API call to aid in ILO trimming.

 

Len
"Engineering is an Art. The Art of Compromise."

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8 Replies
AlenAn14
Moderator
Moderator
Moderator
500 replies posted 100 solutions authored 250 replies posted

Hi @psoc_student ,

Yes, you can trim the ILO clock for better accuracy using the Clock Trim API's provided in the PDL library.
Please refer to the following link to do the same:
https://infineon.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk__trim.html

Warm Regards
Alen

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Alen,

Doesn't the wifi-bt kit already have a watch crystal on-board that can be used for the RTC?

 

Len
"Engineering is an Art. The Art of Compromise."
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The "Wifi Bt Kit" is used for testing and this question is used to build the board itself.

Thank you for your reply.

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psoc_student,

Even ILO trimming will still limit the timing accuracy.  But it will normally help.

Are you familiar with the common method for ILO trimming?

Len
"Engineering is an Art. The Art of Compromise."
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Hello @Len_CONSULTRON 

No, I don't know the details.
Do you have any data or examples to refer to?

Thankyou for your reply

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psoc_student,

Do you have any data or examples to refer to?

If you were working on a PSoC5LP, I would say 'yes'.  I do not have an example on a PSoC6 which as a different clocking structure.

However the principles for the method are the same.

You need to use a more accurate clocking source as your reference to trim the ILO.

You're using the PSoC6 WiFi-BT pioneer kit.   This kit comes with a watch crystal on-board.   You indicated you were going to use the IC but not the kit in production.

I don't know the PSoC6 WiFi-BT kit very well but if you're going to communicate with the WiFi or the Bluetooth resources, you will need a crystal-based clock somewhere in your design.

Once you identify this much more accurate clock, you will need to feed this clock (or a lower division) into a counter with capture capability.   The size of the counter needs to have enough bits of resolution to capture two ILO events.

For example, if your reference clock is 48MHz and the ILO is ~32.768KHz you'll need at least a 16-bit counter.

Connect the your reference clock to the "Clk" input and the ILO clock to the "Capture" input.

Set up the counter as continuous free-running.

(Note:  If you don't want to use HW Capture, you can connect a SW isr to the ILO clock.)

The goal is that the counter value (or capture count) differences between each ILO rising edge should be CLKref/CLKilo = 48MHz/32768Hz = 1464.84 => 1465 counts.  

Algorithm

If the count differences are greater than 1465 then ILO is too slow.  Trim the ILO to raise the clock frequency by one trim value.  

If the count differences are less than 1465 then ILO is too fast.  Trim the ILO to lower the clock frequency by one trim value.  

Repeat the algorithm until you're within one or two counts of the target count difference or you are starting to trim 'oscillate'.

Once you have a working algorithm, you need to decide if this is going to be a continuous trim operation or it is performed occasionally (to adjust for operational temperature differences) or if it is one-time production (one-and-done).    If it is a one-and-done calibration, you will ant to store the trim offset factors into EEPROM, so that if a power interruption occurs, you can reload these trim factors from EEPROM back into the ILO trim registers.

Notes on implementation

Using the counter in continuous mode means that the counter value will wrap.   You need to take this into account when calculating the count difference.   By increasing the counter resolution to 32-bits the wrapping will occur much less often.

The ILO trimming only allows up to a +/- 1.5% accuracy.   Therefore even if your reference clock source is +/- 0.001% you will be limited as to the best accuracy of ILO.

Also consult with the ILO documentation.  Apparently there is a Clock Measurement API call to aid in ILO trimming.

 

Len
"Engineering is an Art. The Art of Compromise."
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Hello @Len_CONSULTRON 

Thank you for your detailed reply.
It was very helpful!

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Hi @psoc_student ,

You can also use the PILO as a clock source for the RTC as this clock source has an accuracy of +-2%.
This accuracy can be further improved by using the clock trim API's but this will require you to use an extremely accurate clock source like the ECO, against which the trimming of the PILO clock (Cy_SysClk_PiloTrim() ) is done.

But you can also alternatively use the IMO (8Mhz , accuracy: +-2%) for the trimming of PILO to +-2% accuracy if using ECO is not an option.

Warm Regards
Alen

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