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PSoC™ 6 Forum Discussions

SaMa_4682226
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

I have a Psoc 6 I2C master.  The desired frequency is 100kHz.  The configuration window says the actual frequency is 96kHz, SCB clock 1548kHz.  With a scope, I'm measuring 49kHz on SCL.

The symptom is occasionally, there is an unexpected extra byte of data received from the slave.  Using a 3rd party I2C tool, the data received is as expected.

What might be wrong? 

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Ekta
Moderator
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250 solutions authored 100 likes received 250 sign-ins

Hi @SaMa_4682226 


@SaMa_4682226 wrote:

I have a Psoc 6 I2C master.  The desired frequency is 100kHz.  The configuration window says the actual frequency is 96kHz, SCB clock 1548kHz.   


The Actual frequency is the actual data rate displays data rate on which component will operate with current settings. This can vary slightly (96kbps in your case). The selected data rate (100kbps) could be differing from actual data rate this is because factors like accuracy of internal component clock affect the actual data rate.

(I assume by desired frequency you mean desired data rate in kbps)


With a scope, I'm measuring 49kHz on SCL.

We tried programming PSoC 6 with the I2C Master application. We observed a  frequency of 96.77kHz at the SCL line as can be seen in the image below:

Ekta_0-1618832589331.png

Can you please let us know if the issue still exists in your case? If so, could you please attach you project?

Also could you please let us know if you are using a custom board?

Thanks and Regards

Ekta

 

 

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6 Replies
Ekta
Moderator
Moderator
Moderator
250 solutions authored 100 likes received 250 sign-ins

Hi @SaMa_4682226 


@SaMa_4682226 wrote:

I have a Psoc 6 I2C master.  The desired frequency is 100kHz.  The configuration window says the actual frequency is 96kHz, SCB clock 1548kHz.   


The Actual frequency is the actual data rate displays data rate on which component will operate with current settings. This can vary slightly (96kbps in your case). The selected data rate (100kbps) could be differing from actual data rate this is because factors like accuracy of internal component clock affect the actual data rate.

(I assume by desired frequency you mean desired data rate in kbps)


With a scope, I'm measuring 49kHz on SCL.

We tried programming PSoC 6 with the I2C Master application. We observed a  frequency of 96.77kHz at the SCL line as can be seen in the image below:

Ekta_0-1618832589331.png

Can you please let us know if the issue still exists in your case? If so, could you please attach you project?

Also could you please let us know if you are using a custom board?

Thanks and Regards

Ekta

 

 

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SaMa_4682226
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Is there a way to privately post?
Thanks.

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SaMa_4682226
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Yes, this is a persistent problem.
Yes, it is a custom board.

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Ekta
Moderator
Moderator
Moderator
250 solutions authored 100 likes received 250 sign-ins

Hi @SaMa_4682226 

I saw the attached project and everything seems to be fine. I saw that the source of all the clocks used in the project is IMO, can you please confirm this? I see that ECO is also enabled. Are you using it anywhere in your project?

Just to make sure that the clocks are working properly can you please try the following:

Drag and drop a PWM in you project, clock it using Clk_peri (48 Mhz as set in the project), set the PWM period as 2 and compare as 1. Observe whether the pwm out has a frequency of 24 Mhz.

 

Ekta_1-1619004705151.png

 

Let me know in case the frequency is not 24 Mhz.

Another thing you can try is programming existing I2C Master project (in psoc creator goto File > Cod example) on your custom board with changing any parameter (just ensure that the correct I2C pins and device has been selected). Check that the frequency that you are observing on the scl pin is the one that is expected.

Ekta_2-1619005573128.png

These two observation will help us to determine if there is some issue at with the software configuration or the hardware.

Thanks and Regards

Ekta

 

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SaMa_4682226
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Ekta,

Modifying the example code, the issue seems to be with the source clock.

If Clk_HF0 = Path 1 (96MHz), SCL is 1/2 of the desired freq. 

If Clk_HF0 = Path 0 (51MHz), things work as expected.

So, it is definitely software.

Also of note, the SCBclk tolerance is 206%. 

 

The actual data rate in the I2C component configuration reports 96kHz in both cases.

 

Thanks.

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SaMa_4682226
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Ekta,
Were you able to reproduce the problem using the modified code example (previously attached)?
Thanks.

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