PSoC62 Vector table in Flash instead of RAM

[Digimorf]

Hello,

I have seen that in many projects for the PSoC62 the startup code for the cm0+ copies the vector table into SRAM, no matter what.

Is there an example that shows how to keep that table in its original position in FLASH?

[LeoMathews · Accepted solution]

Hi @Digimorf 

As of now, there are no code examples that show how to keep that table in its original position in FLASH.  As per PSoC 62 Architecture Technical Reference Manual, in the PSoC 6 MCU, both the vector tables can be configured to be located either in flash memory or SRAM.  The vector table offset register (VTOR) present as part of Cortex-M0+ and Cortex-M4 system control space registers configures the vector table offset from the base address (0x0000).

The CM0P_SCS_VTOR register sets the vector offset address for the CM0+ core and CM4_SCS_VTOR sets the offset for the M4 core. The VTOR value determines whether the vector table is in flash memory (0x10000000 to 0x10100000) or SRAM (0x08000000 to 0x08048000). Note that the VTOR registers can be updated only in privilege CPU mode. The advantage of moving the vector table to SRAM is that the exception handler addresses can be dynamically changed by modifying the SRAM vector table contents. However, the nonvolatile flash memory vector table must be modified by a flash memory write.

Thanks and Regards,
Leo 

[LeoMathews]

Hi @Digimorf  ,

Thread was locked due to inactivity for long time, you can continue the discussion on the topic by opening a new thread with reference to the locked one. The continuous discussion in an inactive thread may mostly be unattended by community users.

Thanks and Regards,
Leo